Apparatus, method and system for a comuter CPU and memory to PCI bridge having a pluarlity of physical PCI buses

Claim 2

A computer system having a core logic chip set capable of bridging between a processor host bus, memory bus and a plurality of peripheral component interconnect (PCI) buses wherein the plurality of PCI buses each have the same logical PCI bus number, said system comprising: a central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chip set connected to the host bus and the random access memory bus; said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus; said core logic chip set configured as a plurality of second interface bridges between the host bus and a plurality of peripheral component interconnect (PCI) buses; said core logic chip set configured as a plurality of third interface bridges between the memory bus and the plurality of PCI buses, wherein the plurality of PCI buses are physically separate but have the same logical PCI bus number; a PCI address comparator; a PCI arbiter for receiving request signals from and issuing grant signals to PCI devices connected to said plurality of PCI buses; and a PCI target flow controller; said PCI address comparator receiving transaction addresses from said plurality of PCI bus interfaces, wherein the transaction addresses are compared and an address match is found if the transaction addresses from two or more of said plurality of PCI bus interfaces are the same or are within M bytes of each other, where M=16×2 n and n is zero or a positive integer number, then said PCI address comparator sends an address match signal to said PCI target flow controller which causes a retry signal to be issued from the one of said plurality of PCI bus interfaces that corresponds to the newest transaction request causing the address match, if the transaction addresses from two or more of said plurality of PCI bus interfaces are not the same nor are the transaction addresses within M bytes then no address match signal is generated.

Claim 3

The computer system of claim 1, wherein the central processing unit is a plurality of central processing units.

Claim 4

The computer system of claim 1, wherein the core logic chip set is at least one integrated circuit.

Claim 5

The computer system of claim 3, wherein the at least one integrated circuit core logic chip set is at least one application specific integrated circuit.

Claim 6

The computer system of claim 3, wherein the at least one integrated circuit core logic chip set is at least one programmable logic array integrated circuit.

Claim 7

The computer system of claim 1, further comprising at least one peripheral component interconnect (PCI) device, the at least one peripheral component interconnect device connected to at least one of the plurality of PCI buses.

Claim 8

The computer system of claim 6, wherein the at least one peripheral component interconnect device is at least one 32 bit data width peripheral component interconnect device.

Claim 9

The computer system of claim 6, wherein the at least one peripheral component interconnect device is at least one 64 bit data width peripheral component interconnect device.

Claim 10

The computer system of claim 6, wherein the at least one peripheral component interconnect device runs at a clock of 66 MHz.

Claim 11

The computer system of claim 1, wherein said plurality of PCI bus interfaces are configured for 32 bit address and data information.

Claim 12

The computer system of claim 1, wherein said plurality of PCI bus interfaces are configured for 64 bit address and data information.

Claim 13

The computer system of claim 6, further comprising a plurality of address range register pairs, wherein a first one of the pair contains a lower memory address and a second one of the pair contains an upper memory address for each of the at least one PCI devices in the computer system.

Claim 14

The computer system of claim 12, further comprising a transaction queue controller, said transaction queue controller comparing current and pending memory transaction addresses with the addresses represented by said plurality of address range register pairs so that when a match is found between the current and pending memory transaction addresses and those addresses represented in said plurality of address range register pairs then strong ordering is used for transaction execution and when a match is not found then weak ordering is used for transaction execution.

Claim 15

The computer system of claim 1, further comprising transaction address filters for each of the plurality of PCI buses, wherein only PCI transactions addressed to a PCI device connected to a one of the plurality of PCI buses is allowed to be broadcast on the one of the plurality of PCI buses.

Claim 16

The computer system of claim 1, further comprising said core logic chip set configured as a plurality of fourth interface bridges between the plurality of PCI buses for peer-to-peer PCI transactions.

Claim 17

The computer system of claim 15, wherein a peer-to-peer PCI transaction is broadcast on only a one of the plurality of PCI buses which is connected to a target PCI device.

Claim 18

The computer system of claim 15, wherein a peer-to-peer PCI transaction is broadcast to a PCI device connected to a one of the plurality of PCI buses through a transaction filter which allows the PCI transaction to be broadcast only on the one of the plurality of PCI buses.

Claim 19

The computer system of claim 15, wherein said plurality of fourth interface bridges is enabled or disabled by setting or clearing a bit in a configuration register of said core logic chip set.

Claim 20

The computer system of claim 15, further comprising logic for asserting a first retry signal on the host bus when a peer-to-peer PCI transaction is pending.

Claim 21

The computer system of claim 19, further comprising logic for determining whether a current transaction on a PCI bus is a first host-to-PCI transaction or a first peer-to-peer PCI transaction, if the current transaction is the first host-to-PCI transaction then the first retry signal is asserted on the host bus when a second peer-to-peer PCI transaction and a second host-to-PCI transaction are pending so that the pending second peer-to-peer PCI transaction executes before the pending second host-to-PCI transaction, if the current transaction is the first peer-to-peer PCI transaction then a second retry signal is asserted on the PCI bus when the second peer-to-peer PCI transaction and the second host-to-PCI transaction are pending so that the pending second host-to-PCI transaction executes before the pending second peer-to-peer PCI transaction.

Claim 22

The computer system of claim 1, wherein the host bus, random access memory bus, and the plurality of PCI buses are on a computer system printed circuit board.

Claim 23

The computer system of claim 21, further comprising at least one set of two PCI connectors, each set of PCI connectors connected to at least one of the plurality of PCI buses.

Claim 24

The computer system of claim 21, further comprising a plurality of sets of two PCI connectors each one of the plurality of sets connected to one of the plurality of PCI buses.

Claim 25

The computer system of claim 21, wherein at least one PCI connector is mounted on the printed circuit board and connected to one of the plurality of PCI buses.

Claim 26

The computer system of claim 1, further comprising said PCI target flow controller generating a wait state signal during comparison of the transaction addresses in said PCI address comparator.

Claim 27

The computer system of claim 1, wherein the PCI target flow controller does not cause the retry signal to be issued if the transaction addresses are only for read transactions.

Claim 28

The computer system of claim 1, wherein the write transactions stored in said plurality of PCI bus read/write queues are flushed before starting the next transaction.

Claim 29

The computer system of claim 1, wherein a plurality of PCI bus transactions may run concurrently between said plurality of PCI bus read/write queues and said random access memory read/write queues.

Claim 30

The computer system of claim 1, wherein said PCI arbiter may issue a grant signal to a requesting PCI device before releasing a grant signal to another PCI device doing a current transaction.

Claim 33

The method of claim 30, further comprising the step of generating a wait state signal during comparison of the transaction addresses in said PCI address comparator.

Claim 34

The method of claim 30, wherein the PCI target flow controller does not cause the retry signal to be issued if the transaction addresses are only for read transactions.

Claim 35

The method of claim 30, wherein peer-to-peer PCI bus transactions occur between said plurality of PCI bus read/write queues.

Claim 36

The method of claim 30, further comprising the steps of: storing a lower memory address in a lower range register associated with a PCI device; storing an upper memory address in an upper range register associated with the PCI device; comparing a transaction memory addresses with a range of addresses between the stored lower and upper memory addresses; using strong ordering for PCI transactions when the transaction memory addresses thereof are found within the range of addresses; and using weak ordering for PCI transactions when the transaction memory addresses thereof are not found within the range of addresses.

Claim 37

The method of claim 30, further comprising the steps of: storing memory and I/O addresses, associated with each PCI device connected to a one of the plurality of PCI buses, in a plurality of transaction address filter registers, each of the plurality of transaction address filter registers associated with a respective one of the plurality of PCI buses; comparing a PCI transaction address with the stored memory and I/O addresses in the plurality of transaction address filter registers to determine which one of the respective one of the plurality of PCI buses the PCI transaction address should be broadcast on.

Claim 40

The method of claim 36, wherein comparing transaction addresses comprises the steps of: detecting a first pending PCI transaction having a second address by a PCI device asserting a transaction request on a one of the plurality of PCI buses; asserting a wait state to the PCI device; and comparing the first pending PCI transaction second address with a current PCI transaction having a first address, comprises the steps of: determining if the first pending PCI transaction second address is for an input-output (I/O) address then waiting for the current PCI transaction to complete before granting the PCI device transaction request; determining if the first pending PCI transaction second address is not a prefetchable memory address then waiting for the current PCI transaction to complete before granting the PCI device transaction request; determining if the first pending PCI transaction second address is the same or is within M bytes of the current PCI transaction first address, where M=16×2 n and n is zero or a positive integer number, then waiting for the current PCI transaction to complete before granting the PCI device transaction request; otherwise, granting the first pending PCI device transaction request before the current PCI transaction has completed.

Claim 41

The method of claim 37, wherein the step of comparing the first pending transaction second address with a current PCI transaction first address further comprises the steps of: determining if the first pending PCI transaction is a peer-to-peer PCI transaction, wherein if the first pending PCI transaction is a peer-to-peer PCI transaction, further comprising the steps of: determining if the current PCI transaction is a peer-to-peer PCI transaction; determining if the current PCI transaction is a host-to-PCI transaction; asserting a first retry signal to the PCI device requesting the first pending PCI transaction if the current PCI transaction is a peer-to-peer transaction and a second pending PCI transaction is a host-to-PCI transaction; otherwise, asserting a second retry signal to the central processing unit connected to the host bus if the current PCI transaction is a host-to-PCI transaction and the second pending PCI transaction is a host-to-PCI transaction; granting the first pending PCI device transaction request; and deasserting the second retry signal to the central processing unit.

Claim 42

The method of claim 37, further comprising the steps of: determining if more than one PCI transaction request is pending, wherein: if only one PCI transaction is pending assert a wait to the PCI device until the current PCI transaction is finished then grant the PCI device transaction request; and if more than one PCI transaction is pending then issue a retry to the last PCI device asserting a transaction request.

Claim 43

The method of claim 36, wherein operation of the PCI arbiter comprises the steps of: detecting a PCI device bus request; determining if the plurality of PCI buses are idle, if so then issuing a grant to the PCI device; determining if concurrent PCI device transactions are permitted, if so then issuing a grant to the PCI device; and determining if the PCI device bus request is on a PCI bus that is idle, if so then issuing a grant to the PCI device; otherwise, waiting until the plurality of PCI buses are idle before issuing a grant to the PCI device.

Claim 44

A core logic chip set capable of bridging between a processor host bus, memory bus and a plurality of peripheral component interconnect (PCI) buses wherein the plurality of PCI buses each have the same logical PCI bus number, comprising: a plurality of PCI bus read/write queues; a plurality of PCI bus interfaces adapted for connection to a plurality of PCI buses; said plurality of PCI bus read/write queues connected to said plurality of PCI bus interfaces, wherein read and write transactions through said plurality of PCI bus interfaces are stored in said plurality of PCI bus read/write queues; processor read/write queues; a processor interface connected to said processor read/write queues, said processor interface adapted for connection to a processor host bus; random access memory read/write queues; a random access memory interface connected to said random access memory read/write queues, said random access memory interface adapted for connection to a random access memory bus; said random access memory queues connected to said processor read/write queues; said plurality of PCI bus read/write queues connected to said random access memory queues; said plurality of PCI bus read/write queues connected to said processor read/write queues; a PCI address comparator; a PCI arbiter adapted for receiving request signals from and issuing grant signals to PCI devices connected to said plurality of PCI buses; and a PCI target flow controller; said PCI address comparator adapted to receive transaction addresses from said plurality of PCI bus interfaces, wherein the transaction addresses are compared and an address match is found if the transaction addresses from two or more of said plurality of PCI bus interfaces are the same or are within M bytes of each other, where M=16×2 n and n is zero or a positive integer number, then said PCI address comparator sends an address match signal to said PCI target flow controller which causes a retry signal to be issued from the one of said plurality of PCI bus interfaces that corresponds to the newest transaction request causing the address match, if the transaction addresses from two or more of said plurality of PCI bus interfaces are not the same nor are the transaction addresses within M bytes then no address match signal is generated.

Claim 45

A core logic chip set capable of bridging between a processor host bus, memory bus and a plurality of peripheral component interconnect (PCI) buses wherein the plurality of PCI buses each have the same logical PCI bus number, comprising: a plurality of PCI bus read/write queues; a plurality of PCI bus interfaces adapted for connection to a plurality of PCI buses; said plurality of PCI bus read/write queues connected to said plurality of PCI bus interfaces, wherein read and write transactions through said plurality of PCI bus interfaces are stored in said plurality of PCI bus read/write queues; processor read/write queues; a processor interface connected to said processor read/write queues, said processor interface adapted for connection to a processor host bus; random access memory read/write queues; a random access memory interface connected to said random access memory read/write queues, said random access memory interface adapted for connection to a random access memory bus; said random access memory queues connected to said processor read/write queues; said plurality of PCI bus read/write queues connected to said random access memory queues; said plurality of PCI bus read/write queues connected to said processor read/write queues; a PCI address comparator; a PCI arbiter adapted for receiving request signals from and issuing grant signals to PCI devices connected to said plurality of PCI buses; and a PCI target flow controller; said PCI address comparator adapted to receive transaction addresses from said plurality of PCI bus interfaces, wherein the transaction addresses are compared and an address match is found if the transaction addresses from two or more of said plurality of PCI bus interfaces are the same or are within M bytes of each other, where M=16×2 n and n is zero or a positive integer number, then said PCI address comparator sends an address match signal to said PCI target flow controller which causes a retry signal to be issued from the one of said plurality of PCI bus interfaces that corresponds to the newest transaction request causing the address match, if the transaction addresses from two or more of said plurality of PCI bus interfaces are not the same nor are the transaction addresses within M bytes then no address match signal is generated.

Claim 46

The core logic chip set according to claim 41, further comprising said PCI target flow controller generating a wait state signal during comparison of the transaction addresses in said PCI address comparator.

Claim 47

The core logic chip set according to claim 41, wherein the PCI target flow controller does not cause the retry signal to be issued if the transaction addresses are only for read transactions.

Claim 48

The core logic chip set according to claim 41, wherein the write transactions stored in said plurality of PCI bus read/write queues are flushed before starting the next transaction.

Claim 49

The core logic chip set according to claim 41, wherein a plurality of PCI bus transactions may run concurrently between said plurality of PCI bus read/write queues and said random access memory read/write queues.

Claim 50

The core logic chip set according to claim 41, wherein said PCI arbiter may issue a grant signal to a requesting PCI device before releasing a grant signal to another PCI device doing a current transaction.

Claim 51

The core logic chip set according to claim 41, wherein said plurality of PCI bus interfaces are configured for 66 megahertz (MHz) operation.

Claim 52

The core logic chip set according to claim 41, wherein said plurality of PCI bus interfaces are adapted for 32 bit address and data information.

Claim 53

The core logic chip set according to claim 41, wherein said plurality of PCI bus interfaces are adapted for 64 bit address and data information.

Claim 54

The core logic chip set according to claim 41, wherein said plurality of PCI bus read/write queues are adapted for peer-to-peer PCI bus transactions occurring therebetween.

Claim 55

The core logic chip set according to claim 41, further comprising: a plurality of range register pairs, said plurality of range register pairs adapted to provide a pair of range registers for each one of a plurality of PCI devices; said plurality of range registers storing upper and lower memory addresses; a transaction queue controller, said transaction queue controller adapted for comparing PCI transaction addresses with addresses between the stored upper and lower memory addresses, when there is a comparison match said transaction queue controller causes strong ordering of PCI transactions, and when there is not a comparison match said transaction queue controller causes weak ordering of PCI transactions.

Claim 56

The core logic chip set according to claim 41, further comprising: transaction address filters connected to each of said plurality of PCI bus read/write queues, wherein only transactions for an intended PCI device reaches an associated one of said plurality of PCI bus read/write queues.

Claim 57

The core logic chip set according to claim 41, further comprising: transaction address filters connected to each of said plurality of PCI bus read/write queues, wherein only transactions for an intended PCI device reaches an associated one of said plurality of PCI bus read/write queues.

Claim 58

The core logic chip set according to claim 41, further comprising: a host processor retry logic adapted for delaying a next host-to-PCI transaction until a pending peer-to-peer PCI transaction has executed.

Claim 59

The core logic chip set according to claim 54, further comprising logic adapted for determining whether a current transaction on a PCI bus is a first host-to-PCI transaction or a first peer-to-peer PCI transaction, if the current transaction is the first host-to-PCI transaction then the first retry signal is asserted on the host bus when a second peer-to-peer PCI transaction and a second host-to-PCI transaction are pending so that the pending second peer-to-peer PCI transaction executes before the pending second host-to-PCI transaction, if the current transaction is the first peer-to-peer PCI transaction then a second retry signal is asserted on the PCI bus when the second peer-to-peer PCI transaction and the second host-to-PCI transaction are pending so that the pending second host-to-PCI transaction executes before the pending second peer-to-peer PCI transaction.