Integrated circuit with temperature detector

Claim 2

An integrated memory device comprising: a temperature detection circuit for tracking a temperature of the integrated memory device and producing an output signal on an output node indicating a temperature range, wherein the temperature detection circuit comprises: a reference circuit for providing a plurality of reference voltages; a temperature sensitive unit for producing a temperature sensitive voltage and a plurality of comparator circuits coupled to the temperature sensitive unit and the reference circuit, each one of the comparator circuits comparing one of the plurality of reference voltages with the temperature sensitive voltage for providing the multiple bit output signal; and a control circuit coupled to the temperature detection circuit for receiving the output signal and adjusting an operation parameter of the integrated circuit memory device in response to the output signal.

Claim 3

The integrated memory device of claim 1 further comprising: a status register for latching the output signal of temperature detection circuit.

Claim 4

The integrated memory device of claim 2 wherein the status register is a volatile latch circuit.

Claim 5

The integrated memory device of claim 1 wherein the output signal is a multiple bit digital output signal.

Claim 6

The integrated memory device of claim 1 wherein the temperature sensitive unit comprises a diode connected between the plurality of comparator circuits and ground potential.

Claim 7

The integrated memory device of claim 5 wherein the diode is fabricated as a transistor having an electrically connected gate and drain.

Claim 8

The integrated memory device of claim 1 wherein the reference circuit comprises: a plurality of series connected resistors connected between a main reference voltage and ground potential.

Claim 9

The integrated memory device of claim 1 wherein the temperature detection circuit further comprises: enable circuitry for resetting the output signal to a predetermined level, and disabling the comparator circuits.

Claim 10

The integrated memory device of claim 8 wherein the enable circuitry further comprises: multiple pull-up transistors connected to multiple output nodes, the pull-up transistors being activated by an enable signal; and disable circuitry connected to the plurality of comparator circuits for disabling the plurality of comparator circuits in response to the enable signal.

Claim 11

The integrated memory device of claim 1 wherein the plurality of comparator circuits are differential circuits.

Claim 12

The integrated memory device of claim 1 wherein the integrated memory device is a flash memory.

Claim 13

The integrated memory device of claim 1 further comprising a non-volatile look-up table for storing data corresponding to output from the temperature detection circuit under known temperature conditions.

Claim 14

An integrated circuit device comprising: a temperature detection circuit for tracking a temperature of the integrated circuit device and producing a multiple-bit output signal indicating a temperature range, wherein the temperature detection circuit comprises: a reference circuit for providing a plurality of reference voltages; a temperature sensitive unit for producing a temperature sensitive voltage; and a plurality of comparator circuits coupled to the temperature sensitive unit and the reference circuit, each one of the comparator circuits comparing one of the plurality of reference voltages with the temperature sensitive voltage for providing the multiple bit output signal; a status register latch circuit for storing the multiple-bit output signal; and a control circuit coupled to the temperature detection circuit and the status register latch circuit, the control circuit adapted to activate the temperature detection circuit and receive the multiple-bit output signal, and adapted to retrieve the multiple-bit output signal from the status register latch circuit.

Claim 15

An integrated circuit device comprising: a temperature detection circuit for tracking a temperature of the integrated circuit device and producing a multiple-bit output signal indicating a temperature range, wherein the temperature detection circuit comprises: a reference circuit for providing a plurality of reference voltages; a temperature sensitive unit for producing a temperature sensitive voltage; and a plurality of comparator circuits coupled to the temperature sensitive unit and the reference circuit, each one of the comparator circuits comparing one of the plurality of reference voltages with the temperature sensitive voltage for providing the multiple bit output signal; a status register latch circuit for storing the multiple-bit output signal; and a control circuit coupled to the temperature detection circuit and the status register latch circuit, the control circuit adapted to activate the temperature detection circuit and receive the multiple-bit output signal, and adapted to retrieve the multiple-bit output signal from the status register latch circuit.

Claim 16

The integrated circuit device of claim 13 further comprising a non-volatile look-up table for storing data corresponding to output from the temperature detection circuit under known temperature conditions.

Claim 17

A flash memory device comprising: an array of non-volatile memory cells; a temperature detection circuit for tracking a temperature of the flash memory device and producing a multiple bit digital output signal on an output node wherein the temperature detection circuit comprises: a reference circuit for providing a plurality of reference voltages; a temperature sensitive diode for producing a temperature sensitive voltage; and a plurality of comparator circuits coupled to the temperature sensitive unit and the reference circuit, each of the comparator circuits comparing one of the plurality of reference voltages with the temperature sensitive voltage for providing the multiple bit output signal; and control circuitry for controlling operation of the flash memory, the control circuit is connected to the temperature detection circuitry for receiving the output signal and adjusting the operation of the flash memory in response thereto.

Claim 18

A flash memory device comprising: an array of non-volatile memory cells; a temperature detection circuit for tracking a temperature of the flash memory device and producing a multiple bit digital output signal on an output node wherein the temperature detection circuit comprises: a reference circuit for providing a plurality of reference voltages; a temperature sensitive diode for producing a temperature sensitive voltage; and a plurality of comparator circuits coupled to the temperature sensitive unit and the reference circuit, each of the comparator circuits comparing one of the plurality of reference voltages with the temperature sensitive voltage for providing the multiple bit output signal; and control circuitry for controlling operation of the flash memory, the control circuit is connected to the temperature detection circuitry for receiving the output signal and adjusting the operation of the flash memory in response thereto.

Claim 19

The flash memory device of claim 15 further comprising: a data look-up table stored in the array of non-volatile memory cells, the data table comprising temperature range data corresponding to temperature detection circuitry output signals under known temperature conditions.

Claim 20

The flash memory device of claim 15 further comprising a data latch circuit for storing the output of the temperature detection circuitry.

Claim 21

The flash memory device of claim 15 wherein the reference circuit comprises a resistor ladder.

Claim 22

The flash memory device of claim 15 wherein the temperature detection circuit further comprises: enable circuitry for resetting the output of the temperature detection circuit to a predetermined level, and disabling the comparator circuits.

Claim 25

The method of claim 20 wherein the step of detecting is performed in response to a command from a control circuit.

Claim 26

The method of claim 20 wherein the generated signal is latched in a latch circuit.

Claim 27

The method of claim 20 further comprising: comparing the generated signal with data stored in a look-up table prior to adjusting the operation of the integrated circuit.

Claim 28

The method of claim 23 further comprising: testing the integrated circuit under known temperature conditions; and storing data in the look-up table based upon test signals generated from the internal temperature detector.

Claim 29

The method of claim 20 further comprising: resetting the generated signal to a predetermined level prior to the step of producing the plurality of first reference voltages.

Claim 30

The method of claim 20 further comprising: providing the generated signal on at least one external output line.

Claim 31

The method of claim 20 wherein the step of adjusting the operation of the integrated circuit comprises: receiving the generated signal on the at least one external output line with an external processor; evaluating the generated signal with the processor; and providing operating control signals to the integrated circuit from the processor.

Claim 32

The method of claim 20 wherein the integrated circuit is a memory device.

Claim 33

A processing system comprising: a controller; a memory device coupled to the controller, the memory device comprising a temperature detection circuit for tracking a temperature of the memory device and producing an output signal on an output node indicating a temperature range, wherein the temperature detection circuit comprises: a reference circuit for providing a plurality of reference voltages; a temperature sensitive unit for producing a temperature sensitive voltage; and a plurality of comparator circuits coupled to the temperature sensitive unit and the reference circuit, each one of the comparator circuits comparing one of the plurality of reference voltages with the temperature sensitive voltage for providing the multiple bit output signal; and a control circuit coupled to the temperature detection circuit for receiving the output signal and adjusting an operation parameter of the memory device in response to the output signal.

Claim 34

A processing system comprising: a controller; a memory device coupled to the controller, the memory device comprising a temperature detection circuit for tracking a temperature of the memory device and producing an output signal on an output node indicating a temperature range, wherein the temperature detection circuit comprises: a reference circuit for providing a plurality of reference voltages; a temperature sensitive unit for producing a temperature sensitive voltage; and a plurality of comparator circuits coupled to the temperature sensitive unit and the reference circuit, each one of the comparator circuits comparing one of the plurality of reference voltages with the temperature sensitive voltage for providing the multiple bit output signal; and a control circuit coupled to the temperature detection circuit for receiving the output signal and adjusting an operation parameter of the memory device in response to the output signal.

Claim 35

The processing system of claim 29 wherein the control circuit is located in the controller, and the output signal is provided on a memory device output connection.

Claim 36

The system of claim 29 wherein the control circuit is located in the memory device.

Claim 39

The method of claim 32 wherein the step of adjusting the operation of the memory device comprises: communicating the generated output signal on at least one external memory device output connection to the controller; evaluating the generated signal with the controller; and providing operating control signals to the memory device from the controller.

Claim 40

The method of claim 32 further including the step of latching the output signal in the memory device.

Claim 41

The method of claim 32 further including the step of latching the output signal in the controller.