US5874860A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High frequency amplifier and control
Assignee: Apple Inc
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Filing: 1996-12-04
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Granted: 1999-02-23
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Expires: 2016-12-04
Abstract
Abstract A monolithic RF amplifier circuit (10) suitable for use in the 0.8-2 GHz frequency range comprises, on-chip (12'), a gateable oscillator (24) running at about 2-5 times the amplifier input frequency or higher, coupled to a rectifier (30) and a low pass filter (34) for producing a DC signal which is fed via a bias/gain control circuit (46) to a bias/gain inputs (56, 58) of one or more amplification stages (60, 62) (e.g. GaAs FET) to provide bias therefore to ensure safe operation, and a priority control circuit (42) responsive to the bias. The priority control circuit (42) operates a power switch (18) that couples the amplification stages (60,62) to a power supply, only when bias is present on their bias/gain inputs (56,58) This protects the amplification stages (60,62) against overcurrent operation. A separate external port (68) to the bias/gain control circuit (46) adjusts the magnitude of the bias to permit amplifier gain and power output to be adjusted. By gating the oscillator ON and OFF, high speed burst mode operation of the amplifier is achieved.
Inventors
- 👤 Dominique Brunel
- 👤 Jacques Trichet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:25
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/52; H03F1/523; H03F1/30; H03F1/305
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
121 words
An amplifier circuit (10) comprising: a DC signal source; an amplification stave (60, 62) using a bias to achieve a predetermined operation; a bias/gain control circuit (46) for receiving the DC signal and providing the bias to the amplification stage (60, 62); and a priority control circuit (42) coupled to the DC source for ensuring that a power supply switch (18) coupling the amplification stage (60, 62) to a terminal (26) of a power supply is only turned ON when the bias is provided wherein gain of the amplification stage (60, 62) depends upon the bias/gain control circuit, wherein the amplifier further comprises an external port whereby the bias and the gain of the amplification stage (60, 62) can be varied.
Claim 2
Dependent Claim
121 words
An amplifier circuit (10) comprising: a DC signal source; an amplification stave (60, 62) using a bias to achieve a predetermined operation; a bias/gain control circuit (46) for receiving the DC signal and providing the bias to the amplification stage (60, 62); and a priority control circuit (42) coupled to the DC source for ensuring that a power supply switch (18) coupling the amplification stage (60, 62) to a terminal (26) of a power supply is only turned ON when the bias is provided wherein gain of the amplification stage (60, 62) depends upon the bias/gain control circuit, wherein the amplifier further comprises an external port whereby the bias and the gain of the amplification stage (60, 62) can be varied.
Claim 3
Dependent Claim
119 words
An amplifier circuit (10) comprising: a DC signal source wherein the DC signal source comprises an oscillator (24) and a rectifier (30); an amplification stage (60, 62) using a bias to achieve a predetermined operation wherein the oscillator (24) operates at a frequency greater than about 2 times an operating frequency of the amplification stage (60, 62); a bias/gain control circuit (46) for receiving the DC signal and providing the bias to the amplification stage (60, 62); and a priority control circuit (42) coupled to the DC source for ensuring that a power supply switch (18) coupling the amplification stage (60, 62) to a terminal (26) of a power supply is only turned ON when the bias is provided.
Claim 4
Dependent Claim
119 words
An amplifier circuit (10) comprising: a DC signal source wherein the DC signal source comprises an oscillator (24) and a rectifier (30); an amplification stage (60, 62) using a bias to achieve a predetermined operation wherein the oscillator (24) operates at a frequency greater than about 2 times an operating frequency of the amplification stage (60, 62); a bias/gain control circuit (46) for receiving the DC signal and providing the bias to the amplification stage (60, 62); and a priority control circuit (42) coupled to the DC source for ensuring that a power supply switch (18) coupling the amplification stage (60, 62) to a terminal (26) of a power supply is only turned ON when the bias is provided.
Claim 5
Dependent Claim
23 words
The amplifier circuit (10) of claim 2 wherein the oscillator (24) operates at a frequency equal to or greater than about 2 GHz.
Claim 6
Dependent Claim
142 words
An amplifier circuit (10) comprising: a DC signal source wherein the DC signal source comprises an oscillator (24); an amplification stage (60, 62) using a bias to achieve a predetermined operation wherein the amplifier has a nominal operating frequency f i and a pass band Δf and the oscillator operates at a frequency f 0 above or below f i such that no significant intermodulation products arising from f i and f 0 appear in the amplifier pass band Δ; a bias/gain control circuit (46) for receiving the DC signal and providing the bias to the amplification stage (60, 62); and a priority control circuit (42) coupled to the DC source for ensuring that a power supply switch (18) coupling the amplification stage (60, 62) to a terminal (26) of a power supply is only turned ON when the bias is provided.
Claim 7
Dependent Claim
142 words
An amplifier circuit (10) comprising: a DC signal source wherein the DC signal source comprises an oscillator (24); an amplification stage (60, 62) using a bias to achieve a predetermined operation wherein the amplifier has a nominal operating frequency f i and a pass band Δf and the oscillator operates at a frequency f 0 above or below f i such that no significant intermodulation products arising from f i and f 0 appear in the amplifier pass band Δ; a bias/gain control circuit (46) for receiving the DC signal and providing the bias to the amplification stage (60, 62); and a priority control circuit (42) coupled to the DC source for ensuring that a power supply switch (18) coupling the amplification stage (60, 62) to a terminal (26) of a power supply is only turned ON when the bias is provided.
Claim 8
Dependent Claim
127 words
An amplifier circuit (10) comprising: a DC signal source wherein the DC signal source comprises an oscillator (24); an amplification stage (60, 62) using a bias to achieve a predetermined operation wherein the amplifier has a nominal operating frequency f i and a pass band Δf and the oscillator operates at an frequency f 0 which is substantially equal to the nominal operating frequency fi; a bias/gain control circuit (46) for receiving the DC signal and providing the bias to the amplification stage (60, 62); and a priority control circuit (42) coupled to the DC source for ensuring that a sower supply switch (18) coupling the amplification stage (60, 62) to a terminal (26) of a power supply is only turned ON when the bias is provided.
Claim 9
Dependent Claim
127 words
An amplifier circuit (10) comprising: a DC signal source wherein the DC signal source comprises an oscillator (24); an amplification stage (60, 62) using a bias to achieve a predetermined operation wherein the amplifier has a nominal operating frequency f i and a pass band Δf and the oscillator operates at an frequency f 0 which is substantially equal to the nominal operating frequency fi; a bias/gain control circuit (46) for receiving the DC signal and providing the bias to the amplification stage (60, 62); and a priority control circuit (42) coupled to the DC source for ensuring that a sower supply switch (18) coupling the amplification stage (60, 62) to a terminal (26) of a power supply is only turned ON when the bias is provided.
Claim 10
Dependent Claim
23 words
The amplifier circuit (10) of claim 1 wherein the amplification stage (60, 62) comprises one or more normally ON depletion mode semiconductor devices.
Claim 11
Dependent Claim
18 words
The amplifier circuit (10) of claim 6 wherein the one or more semiconductor devices comprises an N-channel FET.
Claim 12
Dependent Claim
14 words
The amplifier circuit (10) of claim 7 wherein the FET is a GaAs FET.
Claim 13
Dependent Claim
134 words
A semiconductor based amplifier (12") for amplifying frequency f i when coupled to a power supply (Vb) and a power supply switch (18), CHARACTERIZED BY, an amplification stage (60, 62) for amplifying f i using a bias to achieve a predetermined operation, an oscillator (24) operating at more than about 2 times f i and coupled to a rectifier (30) for producing a DC signal, a bias/gain control circuit (46) for receiving the DC signal and providing the bias to the amplification stages (60, 62), and a priority control circuit (42) coupled to the oscillator (24) and rectifier (30), wherein the priority control circuit (42) operates to ensure that the power supply switch (18) coupling the amplification stage (60, 62) to the power supply (Vb) is only turned ON when the bias is provided.
Claim 14
Dependent Claim
134 words
A semiconductor based amplifier (12") for amplifying frequency f i when coupled to a power supply (Vb) and a power supply switch (18), CHARACTERIZED BY, an amplification stage (60, 62) for amplifying f i using a bias to achieve a predetermined operation, an oscillator (24) operating at more than about 2 times f i and coupled to a rectifier (30) for producing a DC signal, a bias/gain control circuit (46) for receiving the DC signal and providing the bias to the amplification stages (60, 62), and a priority control circuit (42) coupled to the oscillator (24) and rectifier (30), wherein the priority control circuit (42) operates to ensure that the power supply switch (18) coupling the amplification stage (60, 62) to the power supply (Vb) is only turned ON when the bias is provided.
Claim 15
Dependent Claim
43 words
The amplifier circuit of claim 9 wherein gain of the amplification stage (60, 62) depends upon the bias/gain control circuit, wherein the amplifier further comprises an external port whereby the bias and the gain of the amplification stage (60, 62) can be varied.
Claim 16
Dependent Claim
23 words
The amplifier circuit (10) of claim 9 wherein the oscillator (24) operates at a frequency equal to or greater than about 2 GHz.
Claim 17
Dependent Claim
23 words
The amplifier circuit (10) of claim 9 wherein the amplification stage (60, 62) comprises one or more normally ON depletion mode semiconductor devices.
Claim 18
Dependent Claim
18 words
The amplifier circuit (10) of claim 12 wherein the one or more semiconductor devices comprises an N-channel FET.
Claim 19
Dependent Claim
14 words
The amplifier circuit (10) of claim 13 wherein the FET is a GaAs FET.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-22 | 2002-08-24 | 2003-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-22 | 2006-08-24 | 2007-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-22 | 2010-08-24 | 2011-02-23 | $7700.00 | Window Closed / Lapsed |