Semiconductor storage device and method for fabricating the same

Claim 2

A semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer formed therein; a capacitor having a capacitor storage electrode formed on inside walls and a bottom of the first through-hole and connected to the first diffused layer, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a first contact conducting film formed with the same conductive layer forming the capacitor storage electrode, on inside walls and a bottom of the second through-hole and connected to the second diffused layer; a third insulation film formed on the memory cell and having a bit line contact hole formed therein; and a bit line formed on the third insulation film and connected to the first contact conducting film of the memory cell through the bit line contact holes.

Claim 3

A semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer formed therein; a first buried conductor buried on a bottom of the first through-hole and connected to the first diffused layer; a second buried conductor buried on a bottom of the second through-hole and connected to the second diffused layer; a capacitor having a capacitor storage electrode formed on inside walls of the first through-hole and an upper surface of the first buried conductor and connected to the first diffused layer through the first buried conductor, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a first contact conducting film formed with the same conductive layer forming the capacitor storage electrode, on inside walls of the second through-hole and an upper surface of the second buried conductor and connected to the second diffused layer through the second buried conductor; a third insulation film formed on the memory cell and having a bit line contact hole formed therein; and a bit line formed on the third insulation film and connected to the first contact conducting film of the memory cell through the bit line contact hole.

Claim 4

A semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer formed therein; a first buried conductor buried on a bottom of the first through-hole and connected to the first diffused layer; a second buried conductor buried on a bottom of the second through-hole and connected to the second diffused layer; a capacitor having a capacitor storage electrode formed on inside walls of the first through-hole and an upper surface of the first buried conductor and connected to the first diffused layer through the first buried conductor, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a first contact conducting film formed with the same conductive layer forming the capacitor storage electrode, on inside walls of the second through-hole and an upper surface of the second buried conductor and connected to the second diffused layer through the second buried conductor; a third insulation film formed on the memory cell and having a bit line contact hole formed therein; and a bit line formed on the third insulation film and connected to the first contact conducting film of the memory cell through the bit line contact hole.

Claim 5

A semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a second insulation film covering a top of the memory cell transistor, and having a first through-hole opened on the first diffused layer, and a second through-hole opened on the second diffused layer, the first through-hole having an upper portion with a larger opening diameter than a lower portion of the first through-hole; a capacitor having a capacitor storage electrode formed on inside walls and a bottom of the first through-hole with a conductor extending from the lower portion into the upper portion of the first through-hole, spaced apart from the inside walls of the upper portion of the first through-hole, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode, covering at least a part of the capacitor dielectric film; and a first contact conducting film formed on inside walls and a bottom of the second through-hole and connected to the second diffused layer; a third insulation film formed on the memory cell and having a bit line contact hole formed therein; and a bit line formed on the third insulation film and connected to the first contact conductor film of the memory cell through the bit line contact hole.

Claim 6

A semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a second insulation film covering a top of the memory cell transistor, and having a first through-hole opened on the first diffused layer, and a second through-hole opened on the second diffused layer, the first through-hole having an upper portion with a larger opening diameter than a lower portion of the first through-hole; a capacitor having a capacitor storage electrode formed on inside walls and a bottom of the first through-hole with a conductor extending from the lower portion into the upper portion of the first through-hole, spaced apart from the inside walls of the upper portion of the first through-hole, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode, covering at least a part of the capacitor dielectric film; and a first contact conducting film formed on inside walls and a bottom of the second through-hole and connected to the second diffused layer; a third insulation film formed on the memory cell and having a bit line contact hole formed therein; and a bit line formed on the third insulation film and connected to the first contact conductor film of the memory cell through the bit line contact hole.

Claim 7

A semiconductor storage device according to claim 1, wherein the capacitor storage electrode has a first columnar conductor formed in the first through-hole, spaced from the inside walls of the first through-hole; and the first contact conducting film has a second columnar conductor formed in the second through-hole, spaced from the inside walls of the second through-hole.

Claim 8

A semiconductor storage device according to claim 2, wherein the capacitor storage electrode has a first columnar conductor formed in the first through-hole, spaced from the inside walls of the first through-hole; and the first contact conducting film has a second columnar conductor formed in the second through-hole, spaced from the inside walls of the second through-hole.

Claim 9

A semiconductor storage device according to claim 1, wherein that portion of the second insulation film in a region contacting the first insulation film is formed of a material having etching characteristics different from those of the first insulation film.

Claim 10

A semiconductor storage device according to claim 2, wherein that portion of the second insulation film in a region contacting the first insulation film is formed of a material having etching characteristics different from those of the first insulation film.

Claim 11

A semiconductor storage device according to claim 6, wherein the first insulation film is silicon nitride film; and the material having etching characteristics different from those of the first insulation film is silicon oxide film or impurity-doped silicon oxide film.

Claim 12

A semiconductor storage device according to claim 7, wherein the first insulation film is silicon nitride film; and the material having etching characteristics different from those of the first insulation film is silicon oxide film or impurity-doped silicon oxide film.

Claim 13

A semiconductor storage device according to claim 3, wherein the conductor extends in a column-shape into the upper portion of the first through-hole.

Claim 14

A semiconductor storage device according to claim 1, further comprising a sidewall insulation film formed on the inside walls of the bit line contact hole; and the bit line is insulated with respect to the capacitor opposed electrode by the sidewall insulation film.

Claim 15

A semiconductor storage device according to claim 2, further comprising a sidewall insulation film formed on the inside walls of the bit line contact hole; and the bit line is insulated with respect to the capacitor opposed electrode by the sidewall insulation film.

Claim 16

A semiconductor storage device according to claim 3, further comprising a sidewall insulation film formed on the inside walls of the bit line contact hole; and the bit line is insulated with respect to the capacitor opposed electrode by the sidewall insulation film.

Claim 17

A semiconductor storage device according to claim 1, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of a memory cell region where the memory cell is formed, and a wiring layer formed on the second insulation film and formed of the same conducting layer as the bit line; and the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor.

Claim 18

A semiconductor storage device according to claim 2, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of a memory cell region where the memory cell is formed, and a wiring layer formed on the second insulation film and formed of the same conducting layer as the bit line; and the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor.

Claim 19

A semiconductor storage device according to claim 3, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of a memory cell region where the memory cell is formed, and a wiring layer formed on the second insulation film and formed of the same conducting layer as the bit line; and the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor.

Claim 20

A semiconductor storage device according to claim 1, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, a fourth insulation film formed on the bit line, and a wiring layer formed on the fourth insulation film; and in which the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor.

Claim 21

A semiconductor storage device according to claim 2, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, a fourth insulation film formed on the bit line, and a wiring layer formed on the fourth insulation film; and in which the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor.

Claim 22

A semiconductor storage device according to claim 3, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, a fourth insulation film formed on the bit line, and a wiring layer formed on the fourth insulation film; and in which the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor.

Claim 23

A semiconductor storage device according to claim 17, wherein the wiring layer is directly connected to the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistor, the capacitor opposed electrode, or the bit line.

Claim 24

A semiconductor storage device according to claim 18, wherein the wiring layer is directly connected to the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistor, the capacitor opposed electrode, or the bit line.

Claim 25

A semiconductor storage device according to claim 19, wherein the wiring layer is directly connected to the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistor, the capacitor opposed electrode, or the bit line.

Claim 26

A semiconductor storage device according to claim 20, further comprising an etching protection pattern provided directly below the bit line in a region where the bit line and the wiring layer are connected to each other and having the same structure of a laminated film of the capacitor opposed electrode and the third insulation film.

Claim 27

A semiconductor storage device according to claim 21, further comprising an etching protection pattern provided directly below the bit line in a region where the bit line and the wiring layer are connected to each other and having the same structure of a laminated film of the capacitor opposed electrode and the third insulation film.

Claim 28

A semiconductor storage device according to claim 22, further comprising an etching protection pattern provided directly below the bit line in a region where the bit line and the wiring layer are connected to each other and having the same structure of a laminated film of the capacitor opposed electrode and the third insulation film.

Claim 29

A semiconductor storage device according to claim 1, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, and a wiring layer formed on the third insulation film and formed of the same conducting layer as the bit line; and in which the capacitor opposed electrode and the third insulation film are formed extended in a region where the peripheral circuit transistor is formed, and the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor.

Claim 30

A semiconductor storage device according to claim 2, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, and a wiring layer formed on the third insulation film and formed of the same conducting layer as the bit line; and in which the capacitor opposed electrode and the third insulation film are formed extended in a region where the peripheral circuit transistor is formed, and the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor.

Claim 31

A semiconductor storage device according to claim 3, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, and a wiring layer formed on the third insulation film and formed of the same conducting layer as the bit line; and in which the capacitor opposed electrode and the third insulation film are formed extended in a region where the peripheral circuit transistor is formed, and the wiring layer is directly connected to a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor.

Claim 32

A semiconductor storage device according to claim 1, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, and a second contact conductor film formed on inside walls and a bottom of a third through-hole formed in the second insulation film on a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor; and in which the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistors are connected, through the second contact conducting film, to a wiring layer formed on the second insulation film.

Claim 33

A semiconductor storage device according to claim 2, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, and a second contact conductor film formed on inside walls and a bottom of a third through-hole formed in the second insulation film on a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor; and in which the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistors are connected, through the second contact conducting film, to a wiring layer formed on the second insulation film.

Claim 34

A semiconductor storage device according to claim 3, further comprising a peripheral circuit transistor formed on the semiconductor substrate on a periphery of the memory cell region where the memory cell is formed, and a second contact conductor film formed on inside walls and a bottom of a third through-hole formed in the second insulation film on a gate electrode, a first diffused layer or a second diffused layer of the peripheral circuit transistor; and in which the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistors are connected, through the second contact conducting film, to a wiring layer formed on the second insulation film.

Claim 35

A semiconductor storage device according to claim 29, further comprising a third buried conductor formed on a bottom of the third through-hole; and in which the second contact conducting film is connected to the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistor through the third buried conductor.

Claim 36

A semiconductor storage device according to claim 30, further comprising a third buried conductor formed on a bottom of the third through-hole; and in which the second contact conducting film is connected to the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistor through the third buried conductor.

Claim 37

A semiconductor storage device according to claim 31, further comprising a third buried conductor formed on a bottom of the third through-hole; and in which the second contact conducting film is connected to the gate electrode, the first diffused layer or the second diffused layer of the peripheral circuit transistor through the third buried conductor.

Claim 38

A semiconductor storage device according to claim 1, wherein the second insulation film is a laminated film of a plurality of insulation materials having different etching characteristics from each other.

Claim 39

A semiconductor storage device according to claim 2, wherein the second insulation film is a laminated film of a plurality of insulation materials having different etching characteristics from each other.

Claim 40

A semiconductor storage device according to claim 3, wherein the second insulation film is a laminated film of a plurality of insulation materials having different etching characteristics from each other.

Claim 41

A semiconductor storage device according to claim 35, wherein the laminated film comprises a silicon nitride film, and silicon oxide films sandwiching the silicon nitride film.

Claim 42

A semiconductor storage device according to claim 36, wherein the laminated film comprises a silicon nitride film, and silicon oxide films sandwiching the silicon nitride film.

Claim 43

A semiconductor storage device according to claim 37, wherein the laminated film comprises a silicon nitride film, and silicon oxide films sandwiching the silicon nitride film.

Claim 44

A semiconductor storage device according to claim 35, wherein the laminated film comprises a silicon nitride film laid on a silicon oxide film.

Claim 45

A semiconductor storage device according to claim 36, wherein the laminated film comprises a silicon nitride film laid on a silicon oxide film.

Claim 46

A semiconductor storage device according to claim 37, wherein the laminated film comprises a silicon nitride film laid on a silicon oxide film.

Claim 47

A semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer; and a capacitor having a capacitor storage electrode having a contact formed on inside walls and a bottom of the first through-hole and connected to the first diffused layer and have a projection from the contact and extending away from the second insulation film, a capacitor dielectric film formed covering the capacitor storage electrode including both interior and exterior portions of the projection, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film.

Claim 48

A semiconductor storage device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer; and a capacitor having a capacitor storage electrode having a contact formed on inside walls and a bottom of the first through-hole and connected to the first diffused layer and have a projection from the contact and extending away from the second insulation film, a capacitor dielectric film formed covering the capacitor storage electrode including both interior and exterior portions of the projection, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film.

Claim 49

A semiconductor storage device according to claim 44, further comprising a third insulation film formed on the memory cell and having bit line contact hole reaching the second diffused layer through the second insulation film formed in; and a bit line formed on the third insulation film and connected to the second diffused layer of the memory cell through the bit line contact hole.

Claim 50

A semiconductor storage device according to claim 44, in which a second through-hole is formed in the second insulation film and is opened on the second diffused layer; and which further comprises a contact conducting film formed on inside walls and a bottom of the second through-hole and connected to the second diffused layer, and a bit line formed on the memory cell through the third insulation film and connected to the contact conducting film.

Claim 51

A semiconductor storage device according to claim 44, wherein the second insulation film comprises a silicon nitride film and a silicon oxide film; the silicon nitride film is formed on the gate electrode; the silicon oxide film is formed on the silicon nitride film; and the third insulation film comprises a silicon oxide film.

Claim 52

A semiconductor storage device according to claim 1, wherein the first contact conducting film and the capacitor storage electrode are formed of a conducting material which contacts a n-silicon and a p-silicon material.

Claim 53

A semiconductor storage device according to claim 2, wherein the first contact conducting film and the capacitor storage electrode are formed of a conducting material which contacts a n-silicon and a p-silicon material.

Claim 54

A semiconductor storage device according to claim 3, wherein the first contact conducting film and the capacitor storage electrode are formed of a conducting material which contacts a n-silicon and a p-silicon material.

Claim 55

A semiconductor storage device according to claim 44, wherein the capacitor storage electrode are formed of a conducting material which contacts a n-silicon and a p-silicon material.

Claim 56

A semiconductor storage device according to claim 1, wherein the bit line contact hole is elongated in the direction of the bit line.

Claim 57

A semiconductor storage device according to claim 2, wherein the bit line contact hole is elongated in the direction of the bit line.

Claim 58

A semiconductor storage device according to claim 3, wherein the bit line contact hole is elongated in the direction of the bit line.

Claim 59

A semiconductor storage device according to claim 44, wherein the bit line contact hole is elongated in the direction of the bit line.

Claim 60

A semiconductor storage device according to claim 1, wherein the bit line has a film thickness which is below half a gap between the bit line and another bit line.

Claim 61

A semiconductor storage device according to claim 2, wherein the bit line has a film thickness which is below half a gap between the bit line and another bit line.

Claim 62

A semiconductor storage device according to claim 3, wherein the bit line has a film thickness which is below half a gap between the bit line and another bit line.

Claim 63

A semiconductor storage device according to claim 44, wherein the bit line has a film thickness which is below half a gap between the bit line and another bit line.

Claim 64

A semiconductor storage device comprising: a plurality of bit lines arranged parallel with each other; a plurality of word lines arranged parallel with each other and intersecting said plurality of bit lines; sense amplifiers, each of said sense amplifiers disposed on one end of each of the bit lines; decoders, each of said decoders disposed on one end of each of the word lines; and memory cells respectively disposed at intersections of the bit lines and the word lines, each of the memory cells including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer formed therein; a capacitor having a capacitor storage electrode formed on inside walls and a bottom of the first through-hole and connected to the first diffused layer, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a first contact conducting film formed with the same conductive layer forming the capacitor storage electrode, on inside walls and a bottom of the second through-hole and connected to the second diffused layer, said sense amplifiers being divided into two groups, the groups of the sense amplifiers being disposed respectively on opposed sides of a memory cell region where the memory cells are formed, and said decoders being divided into two groups, the groups of the decoders being disposed respectively on opposed sides of the memory cell region where the memory cells are formed.

Claim 65

A semiconductor storage device comprising: a plurality of bit lines arranged parallel with each other; a plurality of word lines arranged parallel with each other and intersecting said plurality of bit lines; sense amplifiers, each of said sense amplifiers disposed on one end of each of the bit lines; decoders, each of said decoders disposed on one end of each of the word lines; and memory cells respectively disposed at intersections of the bit lines and the word lines, each of the memory cells including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer formed therein; a capacitor having a capacitor storage electrode formed on inside walls and a bottom of the first through-hole and connected to the first diffused layer, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a first contact conducting film formed with the same conductive layer forming the capacitor storage electrode, on inside walls and a bottom of the second through-hole and connected to the second diffused layer, said sense amplifiers being divided into two groups, the groups of the sense amplifiers being disposed respectively on opposed sides of a memory cell region where the memory cells are formed, and said decoders being divided into two groups, the groups of the decoders being disposed respectively on opposed sides of the memory cell region where the memory cells are formed.

Claim 66

A semiconductor storage device comprising: a plurality of bit lines arranged parallel with each other; a plurality of word lines arranged parallel with each other and intersection said plurality of bit lines; sense amplifiers, each of said sense amplifiers disposed on one end of each of the bit lines; decoders, each of said decoders disposed on one end of each of the word lines; and memory cells respectively disposed at intersections of the bit lines and the word lines, each of said memory cells including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer formed therein; a first buried conductor buried on a bottom of the first through-hole and connected to the first diffused layer; a second buried conductor buried on a bottom of the second through-hole and connected to the second diffused layer; a capacitor having a capacitor storage electrode formed on inside walls of the first through-hole and an upper surface of the first buried conductor and connected to the first diffused layer through the first buried conductor, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a first contact conducting film formed with the same conductive layer forming the capacitor storage electrode, on inside walls of the second through-hole and an upper surface of the second buried conductor and connected to the second discussed layer through the second buried conductor, said sense amplifiers being divided into two groups, the groups of the sense amplifiers being disposed respectively on opposed sides of a memory cell region where the memory cells are formed, and said decoders being divided into two groups, the groups of the decoders being disposed respectively on opposed sides of the memory cell region where the memory cells are formed.

Claim 67

A semiconductor storage device comprising: a plurality of bit lines arranged parallel with each other; a plurality of word lines arranged parallel with each other and intersection said plurality of bit lines; sense amplifiers, each of said sense amplifiers disposed on one end of each of the bit lines; decoders, each of said decoders disposed on one end of each of the word lines; and memory cells respectively disposed at intersections of the bit lines and the word lines, each of said memory cells including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer formed therein; a first buried conductor buried on a bottom of the first through-hole and connected to the first diffused layer; a second buried conductor buried on a bottom of the second through-hole and connected to the second diffused layer; a capacitor having a capacitor storage electrode formed on inside walls of the first through-hole and an upper surface of the first buried conductor and connected to the first diffused layer through the first buried conductor, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a first contact conducting film formed with the same conductive layer forming the capacitor storage electrode, on inside walls of the second through-hole and an upper surface of the second buried conductor and connected to the second discussed layer through the second buried conductor, said sense amplifiers being divided into two groups, the groups of the sense amplifiers being disposed respectively on opposed sides of a memory cell region where the memory cells are formed, and said decoders being divided into two groups, the groups of the decoders being disposed respectively on opposed sides of the memory cell region where the memory cells are formed.

Claim 68

A semiconductor storage device comprising: a plurality of bit lines arranged parallel with each other; a plurality of word lines arranged parallel with each other and intersection said plurality of bit lines; sense amplifiers, each of said sense amplifiers disposed on one end of each of the word lines; and memory cells respectively disposed at intersections of the bit lines and the word lines, each of said memory cells including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a second insulation film covering a top of the memory cell transistor, and having a first through-hole opened on the first diffused layer, and a second through-hole opened on the second diffused layer, the first through-hole having an upper portion with a larger opening diameter than a lower portion of the first through-hole; a capacitor having a capacitor storage electrode formed on inside walls and a bottom of the first through-hole with a conductor extending from the lower portion into the upper portion of the first through-hole, spaced apart from the inside walls of the upper portion of the first through-hole, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode, covering at least a part of the capacitor dielectric film; and a first contact conducting film formed on inside walls and a bottom of the second through-hole and connected to the second diffused layer, said sense amplifiers being divided into two groups, the groups of the sense amplifiers being disposed respectively on opposed sides of a memory cell region where the memory cells are formed, and said decoders being divided into two groups, the groups of the decoders being disposed respectively on opposed sides of the memory cell region where the memory cells are formed.

Claim 69

A semiconductor storage device comprising: a plurality of bit lines arranged parallel with each other; a plurality of word lines arranged parallel with each other and intersection said plurality of bit lines; sense amplifiers, each of said sense amplifiers disposed on one end of each of the word lines; and memory cells respectively disposed at intersections of the bit lines and the word lines, each of said memory cells including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a second insulation film covering a top of the memory cell transistor, and having a first through-hole opened on the first diffused layer, and a second through-hole opened on the second diffused layer, the first through-hole having an upper portion with a larger opening diameter than a lower portion of the first through-hole; a capacitor having a capacitor storage electrode formed on inside walls and a bottom of the first through-hole with a conductor extending from the lower portion into the upper portion of the first through-hole, spaced apart from the inside walls of the upper portion of the first through-hole, a capacitor dielectric film formed covering the capacitor storage electrode, and a capacitor opposed electrode, covering at least a part of the capacitor dielectric film; and a first contact conducting film formed on inside walls and a bottom of the second through-hole and connected to the second diffused layer, said sense amplifiers being divided into two groups, the groups of the sense amplifiers being disposed respectively on opposed sides of a memory cell region where the memory cells are formed, and said decoders being divided into two groups, the groups of the decoders being disposed respectively on opposed sides of the memory cell region where the memory cells are formed.

Claim 70

A semiconductor storage device comprising: a plurality of bit lines arranged parallel with each other; a plurality of word lines arranged parallel with each other and intersection said plurality of bit lines; sense amplifiers, each of said sense amplifiers disposed on one end of each of the bit lines; decoders, each of said decoders disposed on one end of each of the word lines; and memory cells respectively disposed at intersections of the bit lines and the word lines, each of said memory cells including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer; and a capacitor having a capacitor storage electrode having a contact formed on inside walls and a bottom of the first through-hole and connected to the first diffused layer and have a projection from the contact and extending away from the second insulation film, a capacitor dielectric film formed covering the capacitor storage electrode including both interior and exterior portions of the projection, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film, said sense amplifiers being divided into two groups, the groups of the sense amplifiers being disposed respectively on opposed sides of a memory cell region where the memory cells are formed, and said decoders being divided into two groups, the groups of the decoders being disposed respectively on opposed sides of the memory cell region where the memory cells are formed.

Claim 71

A semiconductor storage device comprising: a plurality of bit lines arranged parallel with each other; a plurality of word lines arranged parallel with each other and intersection said plurality of bit lines; sense amplifiers, each of said sense amplifiers disposed on one end of each of the bit lines; decoders, each of said decoders disposed on one end of each of the word lines; and memory cells respectively disposed at intersections of the bit lines and the word lines, each of said memory cells including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering an upper surface and side surfaces of the gate electrode; a second insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer; and a capacitor having a capacitor storage electrode having a contact formed on inside walls and a bottom of the first through-hole and connected to the first diffused layer and have a projection from the contact and extending away from the second insulation film, a capacitor dielectric film formed covering the capacitor storage electrode including both interior and exterior portions of the projection, and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film, said sense amplifiers being divided into two groups, the groups of the sense amplifiers being disposed respectively on opposed sides of a memory cell region where the memory cells are formed, and said decoders being divided into two groups, the groups of the decoders being disposed respectively on opposed sides of the memory cell region where the memory cells are formed.

Claim 72

A semiconductor storage-device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer; a buried conductor buried in the first through-hole; and a capacitor having a capacitor storage electrode formed on the first insulation film and connected to the first diffused layer through the buried conductor, a capacitor dielectric film formed covering the capacitor storage electrode and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a bit line formed on the first insulation film and connected to the second diffused layer through the second through-hole; the buried conductor and the bit line being formed of the same conducting layer.

Claim 73

A semiconductor storage-device comprising: a memory cell including: a memory cell transistor having a first diffused layer and a second diffused layer formed in a semiconductor substrate, and a gate electrode formed through a gate insulation film on the semiconductor substrate between the first diffused layer and the second diffused layer; a first insulation film covering a top of the memory cell transistor and having a first through-hole opened on the first diffused layer and a second through-hole opened on the second diffused layer; a buried conductor buried in the first through-hole; and a capacitor having a capacitor storage electrode formed on the first insulation film and connected to the first diffused layer through the buried conductor, a capacitor dielectric film formed covering the capacitor storage electrode and a capacitor opposed electrode formed covering at least a part of the capacitor dielectric film; and a bit line formed on the first insulation film and connected to the second diffused layer through the second through-hole; the buried conductor and the bit line being formed of the same conducting layer.

Claim 74

A semiconductor storage device according to claim 64, wherein the buried conductor is formed on sidewalls and a bottom of the first through-hole.

Claim 75

A semiconductor storage device according to claim 64, wherein the first through-hole and the second through-hole are formed spaced outward from the gate electrode.

Claim 76

A semiconductor storage device according to claim 64, wherein an upper surface and side surfaces of the bit line are covered with an insulation film which functions as an etching stopper with respect to a second insulation film formed on the bit line.

Claim 77

A semiconductor storage device according to claim 67, wherein the second insulation film has a third through-hole formed in, the buried conductor being exposed in the third through-hole; and the capacitor dielectric film is formed on sidewalls and a bottom of the third through-hole.