US5872993A
Expired / Lapsed
US
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Communications system with multiple, simultaneous accesses to a memory
Assignee: Microsemi Semiconductor US Inc
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Filing: 1997-12-01
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Granted: 1999-02-16
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Expires: 2017-12-01
Abstract
Abstract The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a microcontroller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.
Inventors
- 👤 Glen W. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:52
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
213 words
A communications system that allows a plurality of simultaneous accesses to a memory, the communications system comprising: a data flow processor (DFP) for managing data transfers; a plurality of processing devices coupled to said DFP that perform data processing; a first processing device; a memory interface coupled to said DFP and to said first processing device; a memory coupled to the memory interface, wherein the memo is operable to store data useable by each of said plurality of processing devices, wherein said DFP selectively allows access to said memory by each of said plurality of processing devices, wherein the memory is operable to store data useable by the first processing device, wherein the memory includes a plurality of memory segments; a plurality of transfer paths, wherein each of said transfer paths is coupled between the memory interface and one of the memory segments, wherein each of the transfer paths provides an independent data transfer path between the memory interface and a respective memory segment; wherein each of the first processing device and the DFP are operable to simultaneously access different memory segments through the memory interface; wherein each of the first processing device and the DFP are operable to select different ones of said transfer paths for simultaneously connecting to different memory segments.
Claim 2
Dependent Claim
213 words
A communications system that allows a plurality of simultaneous accesses to a memory, the communications system comprising: a data flow processor (DFP) for managing data transfers; a plurality of processing devices coupled to said DFP that perform data processing; a first processing device; a memory interface coupled to said DFP and to said first processing device; a memory coupled to the memory interface, wherein the memo is operable to store data useable by each of said plurality of processing devices, wherein said DFP selectively allows access to said memory by each of said plurality of processing devices, wherein the memory is operable to store data useable by the first processing device, wherein the memory includes a plurality of memory segments; a plurality of transfer paths, wherein each of said transfer paths is coupled between the memory interface and one of the memory segments, wherein each of the transfer paths provides an independent data transfer path between the memory interface and a respective memory segment; wherein each of the first processing device and the DFP are operable to simultaneously access different memory segments through the memory interface; wherein each of the first processing device and the DFP are operable to select different ones of said transfer paths for simultaneously connecting to different memory segments.
Claim 3
Dependent Claim
27 words
The communication system of claim 1, wherein said plurality of transfer paths comprises at least three transfer paths and wherein the memory comprises at least three segments.
Claim 4
Dependent Claim
45 words
The communication system of claim 1, wherein the DFP, the memory interface, the memory, and at least a subset of the plurality of processing devices are comprised on a chip and wherein one or more of the processing devices are located external to the chip.
Claim 5
Dependent Claim
16 words
The communication system of claim 1, wherein said plurality of transfer paths comprises eight transfer paths.
Claim 6
Dependent Claim
33 words
The communications system of claim 1, wherein said DFP is programmable to perform data transfers between two or more of said memory segments and two or more of said plurality of processing devices.
Claim 7
Dependent Claim
79 words
The communications system of claim 1, wherein the DFP is coupled to the first processing device, wherein the DFP is operable to provide memory segment access information to the first processing device indicating at least one segment which is to be accessed or released by the DFP, and wherein the first processing device receives the memory segment access information and operates to avoid segment which are being accessed by the DFP as indicated by said memory segment access information.
Claim 8
Dependent Claim
80 words
The communications system of claim 1, wherein the DFP is coupled to the first processing device, wherein the first processing device is operable to provide memory segment access information to the DFP indicating at least one segment which is to be accessed or released by the first processing device; wherein the DFP receives the memory segment access information and operates to avoid segments which are being accessed by the first processing device as indicated by said memory segment access information.
Claim 9
Dependent Claim
70 words
The communications system of claim 1, wherein the DFP is coupled to the first processing device, wherein the first processing device and the DFP are operable to exchange memory segment access information to indicate segments which are to be accessed or released; wherein each of the DFP and the first processing device receives memory segment access information and operates to avoid segments which are being accessed by the other device.
Claim 10
Dependent Claim
183 words
A communications system that allows a plurality of simultaneous accesses to a memory, the communications system comprising: a plurality of processing devices that perform data processing; a memory interface coupled to said plurality of processing devices; a memory coupled to the memory interface, wherein the memory is operable to store data useable by each of said plurality of processing devices, wherein the memory includes a plurality of memory segments; wherein the memory interface selectively provides simultaneous access to the memory by at least two of said plurality of processing devices a plurality of transfer paths, wherein each of said transfer paths is coupled between the memory interface and one of the memory segments, wherein each of the transfer paths provides an independent data transfer path between the memory interface and a respective memory segment; wherein at least two of the plurality of processing devices are operable to simultaneously access different memory segments through the memory interface; wherein at least two of the plurality of processing devices are operable to simultaneously select different ones of said transfer paths for connecting to different memory segments.
Claim 11
Dependent Claim
183 words
A communications system that allows a plurality of simultaneous accesses to a memory, the communications system comprising: a plurality of processing devices that perform data processing; a memory interface coupled to said plurality of processing devices; a memory coupled to the memory interface, wherein the memory is operable to store data useable by each of said plurality of processing devices, wherein the memory includes a plurality of memory segments; wherein the memory interface selectively provides simultaneous access to the memory by at least two of said plurality of processing devices a plurality of transfer paths, wherein each of said transfer paths is coupled between the memory interface and one of the memory segments, wherein each of the transfer paths provides an independent data transfer path between the memory interface and a respective memory segment; wherein at least two of the plurality of processing devices are operable to simultaneously access different memory segments through the memory interface; wherein at least two of the plurality of processing devices are operable to simultaneously select different ones of said transfer paths for connecting to different memory segments.
Claim 12
Dependent Claim
27 words
The communication system of claim 9, wherein said plurality of transfer paths comprises at least three transfer paths and wherein the memory comprises at least three segments.
Claim 13
Dependent Claim
43 words
The communication system of claim 9, wherein the memory interface, the memory, and at least a subset of the plurality of processing devices are comprised on a chip and wherein one or more of the processing devices are located external to the chip.
Claim 14
Dependent Claim
16 words
The communication system of claim 9, wherein said plurality of transfer paths comprises eight transfer paths.
Claim 15
Dependent Claim
34 words
The communications system of claim 9, wherein said memory interface is programmable to perform data transfers between two or more of said memory segments and two or more of said plurality of processing devices.
Claim 16
Dependent Claim
103 words
The communications system of claim 9, further comprising: a first processing device coupled to the memory interface which is operable to access data in the memory; wherein the memory interface is coupled to the first processing device, wherein the memory interface is operable to provide memory segment access information to the first processing device indicating at least one segment which is to be accessed or released by the memory interface, and wherein the first processing device receives the memory segment access information and operates to avoid segments which are being accessed by the memory interface as indicated by said memory segment access information.
Claim 17
Dependent Claim
103 words
The communications system of claim 9, further comprising: a first processing device coupled to the memory interface which is operable to access data in the memory; wherein the memory interface is coupled to the first processing device, wherein the first processing device is operable to provide memory segment access information to the memory interface indicating at least one segment which is to be accessed or released by the first processing device; wherein the memory interface receives the memory segment access information and operates to avoid segments which are being accessed by the first processing device as indicated by said memory segment access information.
Claim 18
Dependent Claim
73 words
The communications system of claim 9, wherein the memory interface is coupled to the first processing device, wherein the first processing device and the memory interface are operable to exchange memory segment access information to indicate segments which are to be accessed or released; wherein each of the memory interface and the first processing device receives memory segment access information and operates to avoid segments which are being accessed by the other device.
Claim 19
Dependent Claim
51 words
The communications system of claim 9, wherein the memory interface comprises a data flow processor (DFP) for managing data transfers, wherein the DFP is coupled to the plurality of processing devices, wherein the DFP selectively provides simultaneous access to the memory by at least two of said plurality of processing devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-15 | 2002-08-17 | 2003-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-15 | 2006-08-17 | 2007-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-15 | 2010-08-17 | 2011-02-16 | $7700.00 | Window Closed / Lapsed |