Arrangement for generating digital signals

Claim 2

A circuit for generating repetitively transmitted signals recurring in a predeterminable time frame, comprising: a write/read memory for storing a plurality of timing data, and a plurality of data items, each timing datum having at least a respective one of said data items corresponding thereto, a counter, means for clocking said counter, means for comparing the content of said counter with a timing datum which is one of said timing data and is read from said memory, and providing a read signal, and addressing means, responsive to said read signal, for reading from said memory the corresponding at least a respective one of said data items.

Claim 3

A circuit as claimed in claim 1, wherein said timing data are times in a first time frame, characterized in that said circuit comprises synchronizing means for synchronizing said means for clocking to signal transmission times in said first time frame, and, in a second time frame asynchronous to said first time frame, for synchronizing said means for clocking to corresponding times in said second time frame.

Claim 4

A circuit as claimed in claim 2, characterized in that said synchronizing means also maintains a reference to said first time frame.

Claim 5

A circuit as claimed in claim 1, characterized in that said plurality of data items includes a respective plurality of category data items in each of a plurality of categories, at least one timing datum has a respective category data item corresponding thereto in each of a plurality of said categories, corresponding category datum items being read simultaneously when a read signal is provided responsive to comparison with said at least one timing datum.

Claim 6

A circuit as claimed in claim 1, characterized in that said timing signals are stored in a time table in said memory, and said memory includes an area for storing said data items, said area being divided into at least two separately selectable sub-areas.

Claim 7

A circuit as claimed in claim 5, characterized in that at least one interrupt signal is stored in one of said sub-areas.

Claim 8

A circuit as claimed in claim 1, characterized in that one of said data items is an interrupt signal.

Claim 9

A circuit for generating repetitively transmitted signals representing data items, and recurring in a predeterminable time frame, for transmission at a transmission bit rate, comprising: a write/read memory for storing a plurality of timing data, and a plurality of said data items, each timing datum having at least a respective one of said data items corresponding thereto, a counter, means for clocking said counter at a rate which is a multiple of said transmission bit rate, means for comparing the content of said counter with a timing datum which is one of said timing data and is read from said memory, and providing a read signal, and addressing means, responsive to said read signal, for reading from said memory the corresponding at least a respective one of said data items.

Claim 10

A circuit for generating repetitively transmitted signals representing data items, and recurring in a predeterminable time frame, for transmission at a transmission bit rate, comprising: a write/read memory for storing a plurality of timing data, and a plurality of said data items, each timing datum having at least a respective one of said data items corresponding thereto, a counter, means for clocking said counter at a rate which is a multiple of said transmission bit rate, means for comparing the content of said counter with a timing datum which is one of said timing data and is read from said memory, and providing a read signal, and addressing means, responsive to said read signal, for reading from said memory the corresponding at least a respective one of said data items.

Claim 11

A circuit as claimed in claim 8 wherein said timing data are times in a first time frame, characterized in that said circuit comprises synchronizing means for synchronizing said means for clocking to signal transmission times in said first time frame, and, in a second time frame asynchronous to said first time frame, for synchronizing said means for clocking to corresponding times in said second time frame.

Claim 12

A circuit as claimed in claim 9, characterized in that said synchronizing means also maintains a reference to said first time frame.

Claim 13

A circuit as claimed in claim 10, characterized in that said plurality of data items includes a respective plurality of category data items in each of a plurality of categories, at least one timing datum has a respective category data item corresponding thereto in each of a plurality of said categories, corresponding category datum items being read simultaneously when a read signal is provided responsive to comparison with said at least one timing datum.

Claim 14

A circuit as claimed in claim 11, characterized in that said timing signals are stored in a time table in said memory, and said memory includes an area for storing said category data items, said area being divided into at least two separately selectable sub-areas.

Claim 15

A circuit as claimed in claim 8, characterized in that at least one interrupt signal is stored in one of said sub-areas.

Claim 16

A radio transceiver for use in a cellular radio transmission system, including a circuit for generating control signals recurring in a predeterminable time frame, comprising: a write/read memory for storing a plurality of timing data, and a plurality of control signals, each timing datum having at least a respective one of said control signals corresponding thereto, and means for selecting and reading from said memory the corresponding at least a respective one of said control signals at a respective time related to each respective stored timing datum, wherein said means for selecting and reading comprises: a counter, means for clocking said counter, means for comparing the content of said counter with a timing datum which is one of said timing data and is read from said memory, and providing a read signal, and addressing means, responsive to said read signal, for reading from said memory the corresponding at least a respective one of said control signals.

Claim 17

A radio transceiver for use in a cellular radio transmission system, including a circuit for generating control signals recurring in a predeterminable time frame, comprising: a write/read memory for storing a plurality of timing data, and a plurality of control signals, each timing datum having at least a respective one of said control signals corresponding thereto, and means for selecting and reading from said memory the corresponding at least a respective one of said control signals at a respective time related to each respective stored timing datum, wherein said means for selecting and reading comprises: a counter, means for clocking said counter, means for comparing the content of said counter with a timing datum which is one of said timing data and is read from said memory, and providing a read signal, and addressing means, responsive to said read signal, for reading from said memory the corresponding at least a respective one of said control signals.

Claim 18

A radio transceiver for use in a cellular radio transmission system, including a circuit for generating control signals recurring in a predeterminable time frame, comprising: a write/read memory for storing a plurality of timing data, and a plurality of control signals, each timing datum having at least a respective one of said control signals corresponding thereto, and means for selecting and reading from said memory the corresponding at least a respective one of said control signals at a respective time related to each respective stored timing datum, wherein said control signals are generated at a clock rate, and said means for selecting and reading comprises a counter, means for clocking said counter at a higher rate which is a multiple of said clock rate, a comparator for comparing the content of said counter with at least one of said timing data and providing a read signal, and an addressing means responsive to the read signal for reading from said memory at least a respective one of said control signals.

Claim 19

A radio transceiver for use in a cellular radio transmission system, including a circuit for generating control signals recurring in a predeterminable time frame, comprising: a write/read memory for storing a plurality of timing data, and a plurality of control signals, each timing datum having at least a respective one of said control signals corresponding thereto, and means for selecting and reading from said memory the corresponding at least a respective one of said control signals at a respective time related to each respective stored timing datum, wherein said control signals are generated at a clock rate, and said means for selecting and reading comprises a counter, means for clocking said counter at a higher rate which is a multiple of said clock rate, a comparator for comparing the content of said counter with at least one of said timing data and providing a read signal, and an addressing means responsive to the read signal for reading from said memory at least a respective one of said control signals.

Claim 20

A transceiver as claimed in claim 15, wherein said respective times are times in a first time frame, characterized in that said circuit comprises means for synchronizing said means for clocking to said times in said first time frame, and for synchronizing said means for clocking to corresponding times in a second time frame asynchronous to said first time frame while maintaining reference to said first time frame.

Claim 21

A transceiver as claimed in claim 15, characterized in that said plurality of control signals includes a respective plurality of category control signals in each of a plurality of categories, at least one timing datum has a respective category control signal corresponding thereto in each of a plurality of said categories, corresponding category control signals being read simultaneously when a read signal is provided responsive to comparison with said at least one timing datum.

Claim 22

A transceiver as claimed in claim 17, characterized in that said timing signals are stored in a time table in said memory, and said memory includes an area for storing said category control signals, said area being divided into at least two separately selectable sub-areas.

Claim 23

A transceiver as claimed in claim 18, characterized in that at least one interrupt signal is stored in one of said sub-areas.

Claim 24

A transceiver as claimed in claim 15, characterized in that said transmission system operates according to a time-division multiple access method.