US5869857A
Expired / Lapsed
US
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CMOS photodetectors with wide range operating region
Assignee: Individual
•
Filing: 1997-04-07
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Granted: 1999-02-09
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Expires: 2017-04-07
Abstract
Abstract A CMOS charge-integration mode photo-detector built on an n-type substrate is disclosed in this invention. This photo-detector includes a p+n photodiode with the n-type substrate constituting an n-region and a p+ diffusion region disposed near a top surface of the n-type substrate, the p+ diffusion region constituting a charge integration node. The photo-detector further includes a gate-biased charge storable n-type MOS transistor functioning as a photo-conversion voltage amplifier supported on the substrate formed with a threshold voltage of Vt0 having a gate terminal connected to the charge integration node. The photo-detector further includes a MOS transistor supported on the substrate functioning as a readout switch transistor having a source terminal connected to a drain terminal of the gate-based charge storable n-type MOS transistor. The photo-detector further includes a pre-charge switch transistor supported on the substrate having a source terminal connected to the charge integration node and a drain terminal connected to a bias voltage source. In an alternate preferred embodiment, the photo-detector is formed in a p-type substrate.
Inventors
- 👤 Pao-Jung Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:20
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/70; H04N25/76; H04N25/77; H04N25/50; H04N25/57; H04N25/60; H04N25/67; H04N25/671; H04N25/677; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/18; H10F39/80; H10F39/803
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
94 words
A CMOS photo-detector supported on a substrate comprising: a p-n junction diode having a charge integration node; a gate-biased charge storable MOS transistor having a gate terminal connected to the charge integration node of said p-n junction diode; a readout switch transistor connected to a drain terminal of said charge storable MOS transistor; and; a bias charge pre-charge switch transistor connected to said charge integration node responsive to a control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor.
Claim 2
Dependent Claim
94 words
A CMOS photo-detector supported on a substrate comprising: a p-n junction diode having a charge integration node; a gate-biased charge storable MOS transistor having a gate terminal connected to the charge integration node of said p-n junction diode; a readout switch transistor connected to a drain terminal of said charge storable MOS transistor; and; a bias charge pre-charge switch transistor connected to said charge integration node responsive to a control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor.
Claim 3
Dependent Claim
28 words
The photo-detector of claim 1 wherein: said source of voltage reference providing said pre-charge bias voltage higher than a threshold voltage of said gate-biased charge storable MOS transistor.
Claim 4
Dependent Claim
56 words
The photo-detector of claim 1 wherein: said p-n junction diode operated according to a plurality of photo-response transfer functions each being substantially linear and corresponding to a threshold voltage Vt0 of said gate-biased charge storable MOS transistor wherein said plurality of photo-response transfer functions covering substantially an entire operating region allowed by a supplied voltage Vdd.
Claim 5
Dependent Claim
22 words
The photo-detector of claim 1 wherein: said substrate is an N-type substrate and said gate-biased charge storable MOS transistor is NMOS transistor.
Claim 6
Dependent Claim
22 words
The photo-detector of claim 1 wherein: said substrate is a P-type substrate and said gate-biased charge storable MOS transistor is PMOS transistor.
Claim 7
Dependent Claim
24 words
The photo-detector of claim 4 wherein: said gate-biased charge storable MOS transistor is a depletion type MOS transistor for providing a negative threshold voltage.
Claim 8
Dependent Claim
41 words
The photo-detector of claim 1 further comprising: a sample and hold capacitor amplifier circuit having a terminal connected to said read-out switch transistor for receiving and holding an output signal, and a sampling-and-hold readout switch transistor for outputting said output signal.
Claim 9
Dependent Claim
102 words
A linear array of photo-detectors supported on a substrate wherein each of said photo-detectors comprising: a p-n junction diode having a charge integration node; a gate-biased charge storable MOS transistor having a gate terminal connected to the charge integration node of said p-n junction diode; a readout switch transistor connected to a drain terminal of said charge storable MOS transistor; and a bias charge pre-charge switch transistor connected to said charge integration node responsive to a preset control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor.
Claim 10
Dependent Claim
102 words
A linear array of photo-detectors supported on a substrate wherein each of said photo-detectors comprising: a p-n junction diode having a charge integration node; a gate-biased charge storable MOS transistor having a gate terminal connected to the charge integration node of said p-n junction diode; a readout switch transistor connected to a drain terminal of said charge storable MOS transistor; and a bias charge pre-charge switch transistor connected to said charge integration node responsive to a preset control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor.
Claim 11
Dependent Claim
36 words
The linear array of photo-detectors of claim 8 wherein: said source of voltage reference of each of said photo-detectors providing said pre-charge bias voltage higher than a threshold voltage of said gate-biased charge storable MOS transistor.
Claim 12
Dependent Claim
30 words
The linear array of photo-detectors of claim 8 wherein: said substrate is an N-type substrate and said gate-biased charge storable MOS transistor of each of said photo-detectors is NMOS transistor.
Claim 13
Dependent Claim
30 words
The linear array of photo-detectors of claim 8 wherein: said substrate is a P-type substrate and said gate-biased charge storable MOS transistor of each of said photo-detectors is PMOS transistor.
Claim 14
Dependent Claim
32 words
The linear array of photo-detectors of claim 10 wherein: said gate-biased charge storable MOS transistor of each of said photo-detectors is a depletion type MOS transistor for providing a negative threshold voltage.
Claim 15
Dependent Claim
97 words
The linear array of photo-detectors of claim 8 further comprising: a digital scanning shift register having a plurality of bits each being connected to a gate terminal of each of said readout switch transistor for sequentially reading out a video signal detected by each of said photo-detectors, and connected to each of said bias charge pre-charge switch transistor for resetting to said voltage reference; and a capacitor-load source follower readout circuit including a buffer amplifier connected to a common source terminal of said readout switch transistor for receiving an output signal sequentially from each of said photo-detectors.
Claim 16
Dependent Claim
102 words
A rectangular array of photo-detectors supported on a substrate wherein each of said photo-detectors comprising: a p-n junction diode having a charge integration node; a gate-biased charge storable MOS transistor having a gate terminal connected to the charge integration node of said p-n junction diode; a readout switch transistor connected to a drain terminal of said charge storable MOS transistor; and a bias charge pre-charge switch transistor connected to said charge integration node responsive to a preset control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor.
Claim 17
Dependent Claim
102 words
A rectangular array of photo-detectors supported on a substrate wherein each of said photo-detectors comprising: a p-n junction diode having a charge integration node; a gate-biased charge storable MOS transistor having a gate terminal connected to the charge integration node of said p-n junction diode; a readout switch transistor connected to a drain terminal of said charge storable MOS transistor; and a bias charge pre-charge switch transistor connected to said charge integration node responsive to a preset control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor.
Claim 18
Dependent Claim
162 words
The rectangular array of photo-detectors of claim 14 further comprising: a vertical digital scanning shift register having a plurality of bits each being connected to a gate terminal of a row of said readout switch transistors of each row of said photo detectors for sequentially activating each of said photo-detectors in said row, and connected to each of said bias charge pre-charge switch transistor for said row of photo-detectors for resetting to said voltage reference; a row of capacitor-load sample-and-hold amplifiers each connected to a common bus of each column of said photo-detectors for sequentially receiving output signals from a row of photo detectors from each column of said rectangular array; and a horizontal digital scanning shift register having a plurality of bits each being connected to a gate terminal of a readout switch transistor of said capacitor-load sample-and-hold amplifiers for sequentially reading out a video signal stored in each of said capacitor-load sample-and-hold amplifiers corresponding to each row of said photo-detectors.
Claim 19
Dependent Claim
133 words
A linear array of photo-detectors supported on a substrate comprising: a p-n junction diode having a charge integration node; a gate-biased charge storable MOS transistor having a gate terminal connected to said charge integration node of said p-n junction diode; a readout switch transistor connected to a drain terminal of said charge storable MOS transistor; a bias pre-charge switch transistor connected to said charge integration node responsive to a control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor; and a sample-and-hold capacitor amplifier circuit having a terminal connected to said readout switch transistor for receiving and holding an output signal from said charge storable MOS transistor, and a sample-and-hold readout switch transistor for outputting said received signal.
Claim 20
Dependent Claim
133 words
A linear array of photo-detectors supported on a substrate comprising: a p-n junction diode having a charge integration node; a gate-biased charge storable MOS transistor having a gate terminal connected to said charge integration node of said p-n junction diode; a readout switch transistor connected to a drain terminal of said charge storable MOS transistor; a bias pre-charge switch transistor connected to said charge integration node responsive to a control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor; and a sample-and-hold capacitor amplifier circuit having a terminal connected to said readout switch transistor for receiving and holding an output signal from said charge storable MOS transistor, and a sample-and-hold readout switch transistor for outputting said received signal.
Claim 21
Dependent Claim
92 words
The linear array of photo-detectors of claim 16 further comprising: a digital scanning shift register having a plurality of bits with each of said bits connected to a gate terminal of each of said sample-and-hold readout switch transistor for sequentially reading out a video signal detected by said each of said photo detectors; and a capacitor load source follower readout circuit including a buffer amplifier connected to a common source terminal of said readout switch transistors of said sample-and-hold amplifiers for sequentially receiving and outputting a video signal from said photo detectors.
Claim 22
Independent Claim
107 words
A method of forming a photo-detector on a substrate comprising: forming a p-n junction diode with a charge integration node; connecting a gate-biased charge storable MOS transistor with a gate terminal connected to said charge integration node of said p-n junction diode, said MOS transistor having a processadjustable threshold voltage; connecting a readout switch transistor to a drain terminal of said charge storable MOS transistor; and connecting a bias charge pre-charge switch transistor to said charge integration node responsive to a preset control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor.
Claim 23
Independent Claim
107 words
A method of forming a photo-detector on a substrate comprising: forming a p-n junction diode with a charge integration node; connecting a gate-biased charge storable MOS transistor with a gate terminal connected to said charge integration node of said p-n junction diode, said MOS transistor having a processadjustable threshold voltage; connecting a readout switch transistor to a drain terminal of said charge storable MOS transistor; and connecting a bias charge pre-charge switch transistor to said charge integration node responsive to a preset control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor.
Claim 24
Dependent Claim
32 words
The method of forming the photo-detector of claim 18 wherein: said source of voltage reference providing said pre-charge bias voltage higher than a threshold voltage of said gate-biased charge storable MOS transistor.
Claim 25
Dependent Claim
22 words
The photo-detector of claim 18 wherein: said substrate is an N-type substrate and said gate-biased charge storable MOS transistor is NMOS transistor.
Claim 26
Dependent Claim
22 words
The photo-detector of claim 18 wherein: said substrate is a P-type substrate and said gate-biased charge storable MOS transistor is PMOS transistor.
Claim 27
Dependent Claim
25 words
The photo-detector of claim 20 wherein: said gate-biased charge storable MOS transistor is a depletion type of MOS transistor for providing a negative threshold voltage.
Claim 28
Dependent Claim
25 words
The photo-detector of claim 21 wherein: said gate-biased charge storable MOS transistor is a depletion type of MOS transistor for providing a positive threshold voltage.
Claim 29
Dependent Claim
119 words
A photo-detector supported on a substrate comprising: a p-n junction diode having a charge integration node; a gate-biased charge storable MOS transistor having a gate terminal connected to said charge integration node of said p-n junction diode; a readout switch transistor connected to a drain terminal of said charge storable MOS transistor; a bias pre-charge switch transistor connected to said charge integration node responsive to a control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor; and a reset witch for resetting said source terminal of said charge storable MOS transistor to a reference voltage during an operating period of said pre-charge switch transistor.
Claim 30
Dependent Claim
119 words
A photo-detector supported on a substrate comprising: a p-n junction diode having a charge integration node; a gate-biased charge storable MOS transistor having a gate terminal connected to said charge integration node of said p-n junction diode; a readout switch transistor connected to a drain terminal of said charge storable MOS transistor; a bias pre-charge switch transistor connected to said charge integration node responsive to a control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor; and a reset witch for resetting said source terminal of said charge storable MOS transistor to a reference voltage during an operating period of said pre-charge switch transistor.
Claim 31
Dependent Claim
24 words
The photo-detector of claim 5 wherein: said gate-biased charge storable MOS transistor is a depletion type MOS transistor for providing a positive threshold voltage.
Claim 32
Dependent Claim
32 words
The linear array of photo-detectors of claim 11 wherein: said gate-biased charge storable MOS transistor of each of said photo-detectors is a depletion type MOS transistor for providing a positive threshold voltage.
Claim 33
Dependent Claim
24 words
The photo-detector of claim 21 wherein: said gate-biased charge storable MOS transistor is a depletion type MOS transistor for providing a positive threshold voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-08 | 2002-08-10 | 2003-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-08 | 2006-08-10 | 2007-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-08 | 2010-08-10 | 2011-02-09 | $7700.00 | Window Closed / Lapsed |