Method of reducing overlap between gate electrode and LDD region

Claim 1

A method of manufacturing an integrated circuit, comprising the steps of: forming a gate electrode on a gate insulator on a semiconductor substrate; implanting a lightly-doped drain (LDD) region in the substrate using the gate electrode as a mask; and removing top and opposing lateral portions of the gate electrode during an etch step after implanting the LDD region.

Claim 2

A method of manufacturing an integrated circuit, comprising the steps of: forming a gate electrode on a gate insulator on a semiconductor substrate; implanting a lightly-doped drain (LDD) region in the substrate using the gate electrode as a mask; and removing top and opposing lateral portions of the gate electrode during an etch step after implanting the LDD region.

Claim 6

A method of manufacturing an integrated circuit so as to reduce overlap between an LDD region and a gate electrode, comprising the steps of: forming a gate electrode on a gate insulator on a semiconductor substrate; implanting a lightly-doped drain (LDD) region in the substrate using the gate electrode as a mask; laterally diffusing the LDD region into the substrate; removing top and opposing lateral portions of the gate electrode during an etch step after implanting the LDD region; and forming a spacer adjacent to an edge of the gate electrode after removing the top and opposing lateral portions.

Claim 7

A method of manufacturing an integrated circuit so as to reduce overlap between an LDD region and a gate electrode, comprising the steps of: forming a gate electrode on a gate insulator on a semiconductor substrate; implanting a lightly-doped drain (LDD) region in the substrate using the gate electrode as a mask; laterally diffusing the LDD region into the substrate; removing top and opposing lateral portions of the gate electrode during an etch step after implanting the LDD region; and forming a spacer adjacent to an edge of the gate electrode after removing the top and opposing lateral portions.

Claim 17

A method of manufacturing a MOSFET so as to reduce overlap between an LDD region and a polysilicon gate, comprising the steps of: providing a silicon substrate doped to a first conductivity type; forming a gate oxide layer on the substrate; depositing a polysilicon layer on the gate oxide layer; anisotropically etching the polysilicon layer to form a polysilicon gate using a dry etch; implanting a lightly-doped drain (LDD) region of a second conductivity type in the substrate using the polysilicon gate as a first implant mask that covers a first region of the substrate, wherein the implanting causes the LDD region to laterally extend within the first region by a first distance; laterally diffusing the LDD region into the substrate by applying heat, wherein the diffusing causes the LDD region to laterally extend within the first region beyond the first distance to a second distance, and the second distance is greater than the first distance; isotropically etching the polysilicon gate using a dry etch that is applied to all of a top surface and first and second opposing lateral edges of the polysilicon gate after implanting the LDD region, thereby removing a top portion and first and second opposing lateral portions of the polysilicon gate and advancing the first and second opposing lateral edges towards one another, wherein the first lateral portion extends within the first region by substantially the second distance; forming an oxide spacer adjacent to and in contact with the first lateral edge of the polysilicon gate after isotropically etching the polysilicon gate; and implanting a heavily-doped region of the second conductivity type in a portion of the LDD region using the polysilicon gate and the spacer as a second implant mask, wherein the heavily-doped region is laterally displaced from the polysilicon gate, and the heavily-doped and LDD regions form a drain.

Claim 18

A method of manufacturing a MOSFET so as to reduce overlap between an LDD region and a polysilicon gate, comprising the steps of: providing a silicon substrate doped to a first conductivity type; forming a gate oxide layer on the substrate; depositing a polysilicon layer on the gate oxide layer; anisotropically etching the polysilicon layer to form a polysilicon gate using a dry etch; implanting a lightly-doped drain (LDD) region of a second conductivity type in the substrate using the polysilicon gate as a first implant mask that covers a first region of the substrate, wherein the implanting causes the LDD region to laterally extend within the first region by a first distance; laterally diffusing the LDD region into the substrate by applying heat, wherein the diffusing causes the LDD region to laterally extend within the first region beyond the first distance to a second distance, and the second distance is greater than the first distance; isotropically etching the polysilicon gate using a dry etch that is applied to all of a top surface and first and second opposing lateral edges of the polysilicon gate after implanting the LDD region, thereby removing a top portion and first and second opposing lateral portions of the polysilicon gate and advancing the first and second opposing lateral edges towards one another, wherein the first lateral portion extends within the first region by substantially the second distance; forming an oxide spacer adjacent to and in contact with the first lateral edge of the polysilicon gate after isotropically etching the polysilicon gate; and implanting a heavily-doped region of the second conductivity type in a portion of the LDD region using the polysilicon gate and the spacer as a second implant mask, wherein the heavily-doped region is laterally displaced from the polysilicon gate, and the heavily-doped and LDD regions form a drain.