Mass data storage controller permitting data to be directly transferred between storage devices without transferring data to main memory and without transferring data over input-output bus

Claim 2

In a computer system having a processor, a main memory, first and second data input-output devices coupled to an input-output bus, and a computer interface bus coupled to the processor, wherein the first and second input-output devices are coupled to first and second secondary buses, respectively, a data device controller comprising: a first device controller coupled to the first and second input-output devices, wherein at least one of the input-output devices is a mass data storage device, and wherein the first device controller is coupled to the computer interface bus and is capable of exchanging data between the processor and each of the first and second input-output devices over the computer interface bus; and a bi-directional data move device connected between the first and second secondary buses, and coupled between the first and second input-output devices and permitting data to be directly transferred between the first and second input-output devices without first transferring the data to the main memory, and without transferring the data over the computer interface bus or over the input-output bus.

Claim 3

The data device controller of claim 1, further comprising a second device controller coupled to the computer interface bus, wherein the first input-output device is coupled to a first data channel and the second input-output device is coupled to a second data channel, wherein the first data channel is coupled to the first device controller, and wherein the second device controller is coupled to the second data channel; wherein the data device controller further comprises a processor interface coupled to the computer interface bus and the first and second device controllers, the processor interface receiving data from and sending data to the processor via the computer interface bus; and wherein the data move device includes a buffer circuit and a data move bus intercoupling the buffer circuit with the first and second device controllers.

Claim 4

The data device controller of claim 1, further comprising a processor interface coupled to the computer interface bus, and wherein the data move device includes a write buffer coupled between the processor interface and the first device controller, a read buffer coupled between the processor interface and the first device controller, and a block move bus coupled between the write buffer and the read buffer.

Claim 5

The data device controller of claim 3, further comprising a second device controller, wherein the processor interface includes first and second bus master circuits, wherein the first input-output device is coupled to a first data channel and the second input-output device is coupled to a second data channel, wherein the first and second data channels are coupled to the first and second device controllers, respectively, wherein the block move bus includes first and second data move buses, and wherein the write and read buffers include: first and second buffer circuits coupled to the first and second device controllers, respectively; a first multiplexer coupled to the first bus master circuit, the computer interface bus, the second data move bus and the first buffer circuit, the first multiplexer selectively coupling the second data move bus to the first buffer circuit responsive to a first routing signal from the first bus master circuit, wherein the first buffer circuit is coupled between the first multiplexer and the first device controller; and a second multiplexer coupled to the second bus master circuit, the computer bus, the first data move bus and the second buffer circuit, the second multiplexer selectively coupling the first data move bus to the second buffer circuit responsive to a second routing signal from the second bus master circuit, and wherein the second buffer circuit is coupled between the second multiplexer and the second device controller.

Claim 6

The data device controller of claim 1, further comprising a processor interface coupled to the computer interface bus, and wherein the data move device includes a data move bus, a multiplexer coupled to the processor interface and the data move bus, and a buffer circuit coupled between the multiplexer and the first device controller, the multiplexer selectively coupling the first data move bus to the first buffer circuit responsive to a routing signal from the processor interface and allowing data from the second input-output device to directly transfer data to the first input-output device.

Claim 7

The data device controller of claim 1 wherein the first and second input-output devices are hard disk drives, and wherein the first device controller is an EIDE-type controller.

Claim 8

The data device controller of claim 1 wherein the first input-output device is a hard disk drive, CD-ROM drive, or tape drive.

Claim 9

In a computer system having a processor, a memory array, first and second data storage devices and a computer interface bus intercoupling the processor, memory array and first and second data storage devices coupled to an input-output bus, and wherein the first and second data storage devices are coupled to first and second secondary buses, respectively, a data storage device controller comprising: a processor interface coupled to the computer bus, the processor interface receiving data from and sending data to the processor via the computer interface bus; a storage device interface coupled to the processor interface and the first and second storage devices via the first and second secondary buses, respectively, and exchanging data between the first storage device and the processor interface and between the second storage device and the processor interface, and wherein at least one of the first and second storage devices is a mass data storage device; a first buffer circuit coupled between the processor interface and the storage device interface; and a first data move bus coupled between the storage device interface and the first buffer circuit, the first data move bus and storage device interface permitting data to be directly transferred between the first and second storage devices, without the data being stored in the memory array and without transferring the data over the input-output bus.

Claim 10

In a computer system having a processor, a memory array, first and second data storage devices and a computer interface bus intercoupling the processor, memory array and first and second data storage devices coupled to an input-output bus, and wherein the first and second data storage devices are coupled to first and second secondary buses, respectively, a data storage device controller comprising: a processor interface coupled to the computer bus, the processor interface receiving data from and sending data to the processor via the computer interface bus; a storage device interface coupled to the processor interface and the first and second storage devices via the first and second secondary buses, respectively, and exchanging data between the first storage device and the processor interface and between the second storage device and the processor interface, and wherein at least one of the first and second storage devices is a mass data storage device; a first buffer circuit coupled between the processor interface and the storage device interface; and a first data move bus coupled between the storage device interface and the first buffer circuit, the first data move bus and storage device interface permitting data to be directly transferred between the first and second storage devices, without the data being stored in the memory array and without transferring the data over the input-output bus.

Claim 11

The data storage device controller of claim 8 wherein the storage device interface includes first and second device controllers, wherein the first storage device is coupled to a first data channel and the second storage device is coupled to a second data channel, and wherein the first and second data channels are coupled to the first and second device controllers, respectively, wherein the processor interface includes first and second bus master circuits, wherein the first storage device is coupled to the first data move bus via the first data channel and first device controller, and wherein the data storage device controller further includes: a second data move bus coupled to the second storage device via the second data channel and second storage device controller; a first multiplexer coupled to the first bus master circuit, the computer bus, the second data move bus and the first buffer circuit, the first multiplexer selectively coupling the second data move bus to the first buffer circuit responsive to a first routing signal from the first bus master circuit, wherein the first buffer circuit is coupled between the first multiplexer and the first device controller; a second buffer circuit coupled to the second device controller; and a second multiplexer coupled to the second bus master circuit, the computer bus, the first data move bus and the second buffer circuit, the second multiplexer selectively coupling the first data move bus to the second buffer circuit responsive to a second routing signal from the second bus master circuit.

Claim 12

The data storage device controller of claim 8, further comprising a multiplexer coupled to the processor interface, the computer bus, the first data move bus and the first buffer circuit, the multiplexer selectively coupling the first data move bus to the first buffer circuit responsive to a routing signal from the processor interface and allowing the second storage device to directly transfer data to the first storage device without routing the data on the computer bus.

Claim 13

The data storage device controller of claim 8 wherein the first and second storage devices are hard disk drives, wherein the data storage device controller is an EIDE-type controller, and wherein the processor interface includes DMA registers for storing DMA commands from the processor to initiate data transfer from the first storage device to the second storage device, without the data first being stored in the memory array.

Claim 14

The data storage device controller of claim 8 wherein the first storage device is a hard disk drive, CD-ROM drive, or tape drive.

Claim 15

In a computer system having a processor, a memory array, first and second data storage devices coupled to an input-output bus and a computer bus coupled to the processor, wherein the first and second data storage devices are coupled to first and second channels, respectively, a data storage device controller comprising: a processor interface coupled to the computer bus and exchanging data between the data storage device controller and the processor via the computer bus; first and second device controllers coupled to the first and second storage devices via the first and second channels, respectively, the first and second device controllers being coupled to the processor interface and exchanging data between the processor interface and the first and second storage devices, and wherein at least one of the first and second storage devices is a mass data storage device; and a first data move bus coupled between the first and second channels, and between first and second device controllers and permitting data to be transferred between the first and second storage devices, without employing the computer bus or the input-output bus and without first transferring the data to the memory array.

Claim 16

In a computer system having a processor, a memory array, first and second data storage devices coupled to an input-output bus and a computer bus coupled to the processor, wherein the first and second data storage devices are coupled to first and second channels, respectively, a data storage device controller comprising: a processor interface coupled to the computer bus and exchanging data between the data storage device controller and the processor via the computer bus; first and second device controllers coupled to the first and second storage devices via the first and second channels, respectively, the first and second device controllers being coupled to the processor interface and exchanging data between the processor interface and the first and second storage devices, and wherein at least one of the first and second storage devices is a mass data storage device; and a first data move bus coupled between the first and second channels, and between first and second device controllers and permitting data to be transferred between the first and second storage devices, without employing the computer bus or the input-output bus and without first transferring the data to the memory array.

Claim 17

The data storage device controller of claim 13 wherein the first storage device is coupled to a first data channel and the second storage device is coupled to a second data channel, and wherein the first and second data channels are coupled to the first and second device controllers, respectively, wherein the processor interface includes first and second bus master circuits, wherein the first storage device is coupled to the first data move bus via the first data channel and first device controller, and wherein the data storage device controller further includes: a first buffer circuit coupled between the processor interface and the first storage device controller; a second data move bus coupled to the second storage device via the second data channel and second storage device controller; a first multiplexer coupled to the first bus master circuit, the computer bus, the second data move bus and the first buffer circuit, the first multiplexer selectively coupling the second data move bus to the first buffer circuit responsive to a first routing signal from the first bus master circuit, wherein the first buffer circuit is coupled between the first multiplexer and the first device controller; a second buffer circuit coupled to the second device controller; and a second multiplexer coupled to the second bus master circuit, the computer bus, the first data move bus and the second buffer circuit, the second multiplexer selectively coupling the first data move bus to the second buffer circuit responsive to a second routing signal from the second bus master circuit.

Claim 18

The data storage device controller of claim 13, further comprising a multiplexer coupled to the processor interface, the computer bus, and the first data move bus, and a first buffer circuit coupled between the first multiplexer and the first device controller, the multiplexer selectively coupling to the first data move bus the first buffer circuit responsive to a routing signal from the processor interface and allowing data from the second storage device to directly transfer data to the first storage device without routing the data on the computer bus.

Claim 19

The data storage device controller of claim 13 wherein the first and second storage devices are hard disk drives, wherein the data storage device controller is an EIDE-type controller, and wherein the processor interface includes DMA registers for storing DMA commands from the processor to initiate data transfer from the first storage device to the second storage device, without first being transferred on the computer bus.

Claim 20

The data storage device controller of claim 13 wherein the first storage device is a hard disk drive, CD-ROM drive, or tape drive.

Claim 21

A computer system comprising: a processor; a memory array; a computer bus intercoupling the processor and the memory array; first and second secondary buses; a first data storage device; a second data storage device, wherein the first and second data storage devices are coupled to the first and second secondary buses, respectively, and wherein at least one of the first and second storage devices is a mass data storage device; an input-output bus coupled to the first and second data storage devices; and a bi-directional data storage device controller comprising: a processor interface coupled to the computer bus and exchanging data between the data storage device controller and the processor via the computer bus; a storage device interface coupled to the processor interface and the first and second storage devices via the first and second secondary buses, respectively, and exchanging data between the first and second storage devices and the processor interface; a first buffer circuit coupled between the processor interface and the storage device interface; and a first data move bus coupled between the storage device interface and the first buffer circuit, the first data move bus and storage device interface permitting data to be directly transferred between the first and second storage devices without transferring the data to the memory array or over the computer bus, or input-output bus.

Claim 22

A computer system comprising: a processor; a memory array; a computer bus intercoupling the processor and the memory array; first and second secondary buses; a first data storage device; a second data storage device, wherein the first and second data storage devices are coupled to the first and second secondary buses, respectively, and wherein at least one of the first and second storage devices is a mass data storage device; an input-output bus coupled to the first and second data storage devices; and a bi-directional data storage device controller comprising: a processor interface coupled to the computer bus and exchanging data between the data storage device controller and the processor via the computer bus; a storage device interface coupled to the processor interface and the first and second storage devices via the first and second secondary buses, respectively, and exchanging data between the first and second storage devices and the processor interface; a first buffer circuit coupled between the processor interface and the storage device interface; and a first data move bus coupled between the storage device interface and the first buffer circuit, the first data move bus and storage device interface permitting data to be directly transferred between the first and second storage devices without transferring the data to the memory array or over the computer bus, or input-output bus.

Claim 23

The computer system of claim 18 wherein the storage device interface includes first and second device controllers, wherein the first storage device is coupled to a first data channel and the second storage device is coupled to a second data channel, and wherein the first and second data channels are coupled to the first and second device controllers, respectively, wherein the processor interface includes first and second bus master circuits, wherein the first storage device is coupled to the first data move bus via the first data channel and first device controller, and wherein the data storage device controller further includes: a second data move bus coupled to the second storage device via the second data channel and second storage device controller; a first multiplexer coupled to the first bus master circuit, the computer bus, the second data move bus and the first buffer circuit, the first multiplexer selectively coupling the second data move bus to the first buffer circuit responsive to a first routing signal from the first bus master circuit, wherein the first buffer circuit is coupled between the first multiplexer and the first device controller; a second buffer circuit coupled to the second device controller; and a second multiplexer coupled to the second bus master circuit, the computer bus, the first data move bus and the second buffer circuit, the second multiplexer selectively coupling the first data move bus to the second buffer circuit responsive to a second routing signal from the second bus master circuit.

Claim 24

The computer system of claim 18, further comprising a multiplexer coupled to the processor interface, the computer bus, the first data move bus and the first buffer circuit, the multiplexer selectively coupling the first data move bus to the first buffer circuit responsive to a routing signal from the processor interface and allowing the second storage device to directly transfer data to the first storage device without routing the data on the computer bus.

Claim 25

The computer system of claim 18 wherein the first and second storage devices are hard disk drives, wherein the data storage device controller is an EIDE-type controller, and wherein the processor interface includes DMA registers for storing DMA commands from the processor to initiate data transfer from the first storage device to the second storage device, without the data first being stored in the memory array.

Claim 26

The computer system of claim 18 wherein the first data storage device is a hard disk drive, CD-ROM drive, or tape drive.