US5866458A
Expired / Lapsed
US
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Method for fabricating a CMOS
Assignee: SK Hynix Inc
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Filing: 1995-08-29
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Granted: 1999-02-02
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Expires: 2015-08-29
Abstract
Abstract A CMOS fabrication method includes the steps of providing a substrate having a surface, forming a first conductive well adjacent to the surface of the substrate, forming a second conductive well adjacent to the surface of the substrate, a portion of the first conductive well overlapping a portion of the second conductive well, forming a field oxide in the overlapping portion of the first and second conductive wells forming a first gate over the first conductive well and a second gate over the second conductive well, masking the first conductive well and implanting second conductive impurities on the second conductive well and masking the second conductive well and implanting first conductive impurities on the first conductive well.
Inventors
- 👤 Chang Jae Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:45
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0188; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
117 words
A CMOS fabrication method comprising the steps of: providing a substrate having a surface; forming a first conductive well adjacent to the surface of the substrate; forming a second conductive well adjacent to the surface of the substrate, a portion of the first conductive well overlapping a portion of the second conductive well; forming a field oxide in the overlapping portion of the first and second conductive wells; forming a first gate over the first conductive well and a second gate over the second conductive well; masking the first conductive well and implanting second conductive impurities on the second conductive well; and masking the second conductive well and implanting first conductive impurities on the first conductive well.
Claim 2
Dependent Claim
117 words
A CMOS fabrication method comprising the steps of: providing a substrate having a surface; forming a first conductive well adjacent to the surface of the substrate; forming a second conductive well adjacent to the surface of the substrate, a portion of the first conductive well overlapping a portion of the second conductive well; forming a field oxide in the overlapping portion of the first and second conductive wells; forming a first gate over the first conductive well and a second gate over the second conductive well; masking the first conductive well and implanting second conductive impurities on the second conductive well; and masking the second conductive well and implanting first conductive impurities on the first conductive well.
Claim 3
Dependent Claim
14 words
The CMOS fabrication method of claim 1, wherein the substrate is formed of silicon.
Claim 4
Dependent Claim
15 words
The CMOS fabrication method of claim 1, wherein the gate is formed of a metal.
Claim 5
Dependent Claim
15 words
The CMOS fabrication method of claim 1, wherein the gate is formed of a polysilicon.
Claim 6
Dependent Claim
25 words
The CMOS fabrication method of claim 1, wherein the step of implating the second conductive impurities controls a channel threshold voltage and a channel stop.
Claim 7
Dependent Claim
23 words
The CMOS fabrication method of claim 1, wherein the step of implanting the second conductive impurities includes the step of implanting boron ions.
Claim 8
Dependent Claim
26 words
The CMOS fabrication method of claim 6, wherein the boron ions are implanted at approximately 3.5×10 12 ions/cm 2 with an energy of approximately 150 KeV.
Claim 9
Dependent Claim
25 words
The CMOS fabrication method of claim 1, wherein the step of implanting the first conductive impurities controls a channel threshold voltage and a channel stop.
Claim 10
Dependent Claim
28 words
The CMOS fabrication method of claim 1, wherein the step of implanting the first conductive impurities includes the step of implanting phosphorus ions to the first conductive well.
Claim 11
Dependent Claim
26 words
The CMOS fabrication method of claim 9, wherein the boron ions are implanted at approximately 3.0×10 12 ions/cm 2 with an energy of approximately 150 KeV.
Claim 12
Dependent Claim
99 words
A CMOS fabrication method comprising the steps of: providing a substrate having a surface; forming a first conductive well adjacent to the surface of the substrate; forming a second conductive well adjacent to the surface of the substrate, a portion of the first conductive well overlapping a portion of the second conductive; forming a field oxide in the overlapping portion; forming a first gate over the first conductive well and a second gate over the second conductive well; selectively implanting second conductive impurities into the second conductive well; and selectively implanting first conductive impurities into the first conductive well.
Claim 13
Dependent Claim
99 words
A CMOS fabrication method comprising the steps of: providing a substrate having a surface; forming a first conductive well adjacent to the surface of the substrate; forming a second conductive well adjacent to the surface of the substrate, a portion of the first conductive well overlapping a portion of the second conductive; forming a field oxide in the overlapping portion; forming a first gate over the first conductive well and a second gate over the second conductive well; selectively implanting second conductive impurities into the second conductive well; and selectively implanting first conductive impurities into the first conductive well.
Claim 14
Dependent Claim
14 words
The CMOS fabrication method of claim 11, wherein the substrate is formed of silicon.
Claim 15
Dependent Claim
15 words
The CMOS fabrication method of claim 7, wherein the gate is formed of a metal.
Claim 16
Dependent Claim
14 words
The CMOS fabrication method of claim 11, wherein the gate is formed of polysilicon.
Claim 17
Dependent Claim
25 words
The CMOS fabrication method of claim 11, wherein the step of selectively implanting the second conductive impurities controls a threshold voltage and a channel stop.
Claim 18
Dependent Claim
24 words
The CMOS fabrication method of claim 11, wherein the step of selectively implanting the second conductive impurities includes the step of implanting boron ions.
Claim 19
Dependent Claim
26 words
The CMOS fabrication method of claim 16, wherein the boron ions are implanted at approximately 3.5×10 12 ions/cm 2 with an energy of approximately 150 KeV.
Claim 20
Dependent Claim
25 words
The CMOS fabrication method of claim 11, wherein the step of selectively implanting the first conductive impurities controls a threshold voltage and a channel stop.
Claim 21
Dependent Claim
24 words
The CMOS fabrication method of claim 11, wherein the step of selectively implanting the first conductive impurities includes the step of implanting phosphorus ions.
Claim 22
Dependent Claim
26 words
The CMOS fabrication method of claim 19, wherein the phosphorus ions are implanted at substantially 3.0×10 12 ions/cm 2 with an energy of approximately 150 KeV.
References Cited (Backward Citations)
US5292671A
Cited
US5208473A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-02-01 | 2002-08-03 | 2003-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-01 | 2006-08-03 | 2007-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-01 | 2010-08-03 | 2011-02-02 | $7700.00 | Window Closed / Lapsed |