US5861670A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device package
Assignee: Fujitsu Ltd
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Filing: 1996-05-21
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Granted: 1999-01-19
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Expires: 2016-05-21
Abstract
Abstract An integrated circuits package or a chip carrier having an integrated circuits chip sealed therein comprises layers of ceramic substrates, and terminal steps which are connected to inner pads in contact with the integrated circuits chip and which are provided on the bottom surface of at least one layer of the package, preferably the lowermost layer. The terminal steps are provided in a lattice arrangement, with so many rows of terminal steps as equals the number of terminal steps in one row, thus enabling connection of all of the terminals of the chip to outside wirings, such as wirings of a mother board.
Inventors
- 👤 Hidehiko Akasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:43
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/657; H10W70/67; H10W70/68; H10W70/685; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H05K3/3436; H10W70/654; H10W70/655; H10W70/656; H10W70/682; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
291 words
An integrated circuit chip package comprising: an integrated circuit chip having a generally planar major surface; a stack of substrate layers formed from an electrically insulating material, said layers being arranged in said stack as parallel laminations with an upper substrate layer on top of the stack and a lower substrate layer at the bottom of the stack, said layers each having generally planar upper and lower surfaces and a number of via holes therethrough, the upper surface of one of said substrate layers providing a die pad area, said chip being mounted at said die pad area with its said major surface disposed in general parallelism to said substrate layers; a plurality of electrodes formed on the upper surface of the upper substrate layer; a series of wires electrically interconnecting said electrodes and said chip; a plurality of rows of solder bumps formed in a grid like array on the lower surface of the lower substrate layer, said solder bumps being arranged to reflow for direct connection to corresponding terminals of a circuit board, said solder bumps being distributed on the lower surface of the lower substrate layer including an area directly beneath said die pad area, whereby at least four of the solder bumps are located directly beneath said die pad area; a plurality of wiring elements formed between the substrate layers; a plurality of metalizing components formed in respective selected ones of said via holes, said wiring elements and said selected via holes being arranged so that said solder bumps and said electrodes are connected together only through said selected via holes; and a sealing component attached to said package above the upper substrate layer and comprising a sealing resin covering and providing a seal for said chip.
Claim 2
Dependent Claim
291 words
An integrated circuit chip package comprising: an integrated circuit chip having a generally planar major surface; a stack of substrate layers formed from an electrically insulating material, said layers being arranged in said stack as parallel laminations with an upper substrate layer on top of the stack and a lower substrate layer at the bottom of the stack, said layers each having generally planar upper and lower surfaces and a number of via holes therethrough, the upper surface of one of said substrate layers providing a die pad area, said chip being mounted at said die pad area with its said major surface disposed in general parallelism to said substrate layers; a plurality of electrodes formed on the upper surface of the upper substrate layer; a series of wires electrically interconnecting said electrodes and said chip; a plurality of rows of solder bumps formed in a grid like array on the lower surface of the lower substrate layer, said solder bumps being arranged to reflow for direct connection to corresponding terminals of a circuit board, said solder bumps being distributed on the lower surface of the lower substrate layer including an area directly beneath said die pad area, whereby at least four of the solder bumps are located directly beneath said die pad area; a plurality of wiring elements formed between the substrate layers; a plurality of metalizing components formed in respective selected ones of said via holes, said wiring elements and said selected via holes being arranged so that said solder bumps and said electrodes are connected together only through said selected via holes; and a sealing component attached to said package above the upper substrate layer and comprising a sealing resin covering and providing a seal for said chip.
Claim 3
Dependent Claim
266 words
An integrated circuit chip package comprising: an integrated circuit chip having a generally planar major surface; a substrate layer formed from an electrically insulating material, said layer having generally planar upper and lower surfaces and a number of via holes therethrough, the upper surface of said substrate layer providing a die pad area, said chip being mounted at said area of the substrate layer with its said major surface disposed in general parallelism to the upper and lower surfaces of said substrate layer; a plurality of electrodes formed on the upper surface of said substrate layer; a series of wires electrically interconnecting said electrodes and said chip; a plurality of rows of solder bumps formed in a grid like array on the lower surface of said substrate layer, said solder bumps being arranged to reflow for direct connection to corresponding terminals of a circuit board, said solder bumps being distributed on the lower surface of said substrate layer including an area directly beneath said die pad area, whereby at least four of the solder bumps are located directly beneath said die pad area; a plurality of wiring elements formed between the upper and lower surfaces of the substrate layer; a plurality of metalizing components formed in respective selected ones of said via holes, said wiring elements and said selected via holes being arranged so that said solder bumps and said desired electrodes are connected together only through said selected via holes; and a sealing component attached to said package above said substrate layer and comprising a sealing resin covering and providing a seal for said chip.
Claim 4
Dependent Claim
266 words
An integrated circuit chip package comprising: an integrated circuit chip having a generally planar major surface; a substrate layer formed from an electrically insulating material, said layer having generally planar upper and lower surfaces and a number of via holes therethrough, the upper surface of said substrate layer providing a die pad area, said chip being mounted at said area of the substrate layer with its said major surface disposed in general parallelism to the upper and lower surfaces of said substrate layer; a plurality of electrodes formed on the upper surface of said substrate layer; a series of wires electrically interconnecting said electrodes and said chip; a plurality of rows of solder bumps formed in a grid like array on the lower surface of said substrate layer, said solder bumps being arranged to reflow for direct connection to corresponding terminals of a circuit board, said solder bumps being distributed on the lower surface of said substrate layer including an area directly beneath said die pad area, whereby at least four of the solder bumps are located directly beneath said die pad area; a plurality of wiring elements formed between the upper and lower surfaces of the substrate layer; a plurality of metalizing components formed in respective selected ones of said via holes, said wiring elements and said selected via holes being arranged so that said solder bumps and said desired electrodes are connected together only through said selected via holes; and a sealing component attached to said package above said substrate layer and comprising a sealing resin covering and providing a seal for said chip.
Claim 5
Dependent Claim
236 words
An integrated circuit chip package comprising: an integrated circuit chip having a generally planar major surface; a stack of substrate layers formed from an electrically insulating material, said layers being arranged in said stack as parallel laminations, said layers each having generally planar upper and lower surfaces, there being a number of via holes formed in said stack, said chip being mounted at a die pad area with its said major surface disposed in general parallelism relative to said substrate layers; a plurality of electrodes formed on the substrate layers; a series of electrical interconnections connecting said electrodes and said chip; a plurality of rows of solder bumps formed in a grid like array on the lower surface of the lowermost substrate layer of the stack, said solder bumps being arranged to reflow for direct connection to corresponding terminals of a circuit board, said solder bumps being distributed substantially throughout the said lower surface of said lowermost substrate layer including an area directly beneath said die pads whereby at least four of the solder bumps are located directly beneath said die pad; a plurality of wiring elements formed between layers of the stack; and a plurality of metalizing components formed in respective selected ones of said via holes, said wiring elements and said selected via holes being arranged so that said solder bumps and said desired electrodes are connected together only through said selected via holes.
Claim 6
Dependent Claim
236 words
An integrated circuit chip package comprising: an integrated circuit chip having a generally planar major surface; a stack of substrate layers formed from an electrically insulating material, said layers being arranged in said stack as parallel laminations, said layers each having generally planar upper and lower surfaces, there being a number of via holes formed in said stack, said chip being mounted at a die pad area with its said major surface disposed in general parallelism relative to said substrate layers; a plurality of electrodes formed on the substrate layers; a series of electrical interconnections connecting said electrodes and said chip; a plurality of rows of solder bumps formed in a grid like array on the lower surface of the lowermost substrate layer of the stack, said solder bumps being arranged to reflow for direct connection to corresponding terminals of a circuit board, said solder bumps being distributed substantially throughout the said lower surface of said lowermost substrate layer including an area directly beneath said die pads whereby at least four of the solder bumps are located directly beneath said die pad; a plurality of wiring elements formed between layers of the stack; and a plurality of metalizing components formed in respective selected ones of said via holes, said wiring elements and said selected via holes being arranged so that said solder bumps and said desired electrodes are connected together only through said selected via holes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-18 | 2002-07-20 | 2003-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-18 | 2006-07-20 | 2007-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-18 | 2010-07-20 | 2011-01-19 | $7700.00 | Window Closed / Lapsed |