Memory interface apparatus including an address modification unit having an offset table for prestoring a plurality of offsets

Claim 2

A memory interface apparatus, comprising: an access unit responsive to reception of a data packet including at least one operation code, an address and data for accessing a plurality of prescribed addresses of a storage unit; and a processing unit, wherein said access unit includes storage unit address modifying means having a plurality of offset memories for pre-storing a plurality of offsets, and according to one of said at least one operation code in said received data packet, reading said offset from each of said plurality of offset memories based on said data of said received data packet and modifying said address of said received data packet using said plurality of offsets which have been read or modifying said address of said received data packet using said data of said received data packet, and outputting said plurality of prescribed addresses based on a result of said modification, and storage unit accessing means for accessing, according to said one operation code of said received data packet, said plurality of prescribed addresses of said storage unit output from said storage unit address modifying means, and said processing unit includes operation means for performing, according to said one operation code of said received data packet, operation of a result of access to said plurality of prescribed addresses by said storage unit accessing means and said data of said received data packet.

Claim 3

The memory interface apparatus according to claim 1, wherein said storage unit accessing means updates, using a result of said operation by said operation means, a content of said plurality of prescribed addresses of said storage unit output from said storage unit address modifying means, when said operation code of said received data packet indicates update of a content of said storage unit.

Claim 4

The memory interface apparatus according to claim 2, wherein when said storage unit includes a plurality of data memories which are accessed in parallel respectively based on said plurality of prescribed addresses, said storage unit address modifying means includes memory address modifying means respectively corresponding to said plurality of data memories, and said storage unit accessing means includes memory accessing means respectively corresponding to said plurality of data memories, each of said memory address modifying means includes offset table for pre-storing a plurality of said offsets, and according to said operation code of said received data packet, reads said offsets from said offset table based on said data of said received data packet, modifies said address of said received data packet using either said data of said received data packet or said offset read from said offset table, and outputs said modified address as said prescribed address, and each of said memory accessing means accesses, according to said operation code of said received data packet, said prescribed address of corresponding one of said data memories output from corresponding one of said memory address modifying means.

Claim 5

The memory interface apparatus according to claim 3, wherein each of said memory address modifying means includes adding means for adding, according to said operation code of said received data packet, either said data of said received data packet or said offset read from said offset table and said address of said received data packet, and translating means for translating a result of said addition into said prescribed address.

Claim 6

The memory interface apparatus according to claim 2, wherein said storage unit address modifying means includes address sequential modification means having a plurality of offset tables for pre-storing a plurality of said offsets, and according to said operation code of said received data packet, sequentially reading said offset from each of said plurality of offset tables based on said data of said received data packet, sequentially modifying said address of said received data packet using either said offset which has been read or said data of said received data packet every time said offset is sequentially read, and sequentially outputting said sequentially modified address as said prescribed address, said storage unit accessing means includes sequential access for sequentially accessing, according to said operation code of said received data packet, said prescribed address sequentially output from said address sequential modification means, and said operation means includes accumulation operation means for sequentially receiving a result of said access by said sequential access means, and performing, according to said operation code of said received data packet, sequential operation of data of said received data packet or a sequentially received result of said access with each operation result accumulated.

Claim 7

The memory interface apparatus according to claim 5, wherein said address sequential modification means includes adding means for adding, according to said operation code of said received data packet, said offset which has been read or said data of said received data packet to said address of said received data packet to sequentially output a result of addition every time said offset is sequentially read from said plurality of offset tables, and translating means for translating said result of addition sequentially output from said adding means into said prescribed address.

Claim 8

The memory interface apparatus according to claim 5, wherein said storage unit address modifying means further includes control means for controlling, for sequential read of said offset, each of said plurality of offset tables to be accessed based on said data of said received data packet in a time-sharing manner.

Claim 9

The memory interface apparatus according to claim 1, wherein when said storage unit includes a plurality of data memories which are accessed in parallel respectively based on said plurality of prescribed addresses, said storage unit address modifying means includes memory address modifying means respectively corresponding to said plurality of data memories, and said storage unit accessing means includes memory accessing means respectively corresponding to said plurality of data memories, each of said memory address modifying means includes an offset table for pre-storing a plurality of said offsets, and according to said operation code of said received data packet, reads said offsets from said offset table based on said data of said received data packet, modifies said address of said received data packet using either said data of said received data packet or said offset read from said offset table, and outputs said modified address as said prescribed address, and each of said memory accessing means accesses, according to said operation code of said received data packet, said prescribed address of corresponding one of said data memories output from corresponding one of said memory address modifying means.

Claim 10

The memory interface apparatus according to claim 8, wherein each of said memory address modifying means includes adding means for adding, according to said operation code of said received data packet, either said data of said received data packet or said offset read from said offset table and said address of said received data packet, and translating means for translating a result of said addition into said prescribed address.

Claim 11

The memory interface apparatus according to claim 1, wherein said storage unit address modifying means includes address sequential modification means having a plurality of offset tables for pre-storing a plurality of said offsets, and according to said operation code of said received data packet, sequentially reading said offset from each of said plurality of offset tables based on said data of said received data packet, sequentially modifying said address of said received data packet using either said offset which has been read or said data of said received data packet every time said offset is sequentially read, and sequentially outputting said sequentially modified address as said prescribed address, said storage unit accessing means includes sequential access for sequentially accessing, according to said operation code of said received data packet, said prescribed address sequentially output from said address sequential modification means, and said operation means includes accumulation operation means for sequentially receiving a result of said access by said sequential access means, and performing, according to said operation code of said received data packet, sequential operation of data of said received data packet or a sequentially received result of said access with each operation result accumulated.

Claim 12

The memory interface apparatus according to claim 10, wherein said address sequential modification means includes adding means for adding, according to said operation code of said received data packet, said offset which has been read or said data of said received data packet to said address of said received data packet to sequentially output a result of addition every time said offset is sequentially read from said plurality of offset tables, and translating means for translating said result of addition sequentially output from said adding means into said prescribed address.

Claim 13

The memory interface apparatus according to claim 10, wherein said storage unit address modifying means further includes control means for controlling, for sequential read of said offset, each of said plurality of offset tables to be accessed based on said data of said received data packet in a time-sharing manner.

Claim 14

The memory interface apparatus according to claim 1, wherein said data of said data packet includes modification data used for said modification by said storage unit address modifying means, and operation data used for said operation by said operation means.

Claim 15

The memory interface apparatus according to claim 1, wherein said storage unit stores image data, and said operation is used for filter operation or correlation operation of said image data.

Claim 16

The memory interface apparatus according to claim 1, wherein the memory interface apparatus receives said data packet in a time series order according to a scanning order of said image, and said address is assigned to said received data packet in an input time series order.

Claim 17

The memory interface apparatus according to claim 1, wherein said memory interface apparatus is provided in a data driven processor.

Claim 18

The memory interface apparatus according to claim 1, further comprising offset determining means for controlling whether said address of said received data packet is modified based on said plurality of offsets or said data of said received data packet.

Claim 19

A memory interface apparatus, comprising: an access unit responsive to reception of a data packet including at least one operation code, an address and data for accessing a plurality of prescribed addresses of a storage unit; and a processing unit, wherein said access unit includes storage unit address modifying device having a plurality of offset memories for pre-storing a plurality of offsets, and according to one of said at least one operation code in said received data packet, reading said offset from each of said plurality of offset memories based on said data of said received data packet and modifying said address of said received data packet using said plurality of offsets which have been read or modifying said address of said received data packet using said data of said received data packet, and outputting said plurality of prescribed addresses based on a result of said modification, and storage unit accessing device for accessing, according to said one operation code of said received data packet, said plurality of prescribed addresses of said storage unit output from said storage unit address modifying device, and said processing unit includes operation device for performing, according to said one operation code of said received data packet, operation of a result of access to said plurality of prescribed addresses by said storage unit accessing device and said data of said received data packet.

Claim 20

A memory interface apparatus, comprising: an access unit responsive to reception of a data packet including at least one operation code, an address and data for accessing a plurality of prescribed addresses of a storage unit; and a processing unit, wherein said access unit includes storage unit address modifying device having a plurality of offset memories for pre-storing a plurality of offsets, and according to one of said at least one operation code in said received data packet, reading said offset from each of said plurality of offset memories based on said data of said received data packet and modifying said address of said received data packet using said plurality of offsets which have been read or modifying said address of said received data packet using said data of said received data packet, and outputting said plurality of prescribed addresses based on a result of said modification, and storage unit accessing device for accessing, according to said one operation code of said received data packet, said plurality of prescribed addresses of said storage unit output from said storage unit address modifying device, and said processing unit includes operation device for performing, according to said one operation code of said received data packet, operation of a result of access to said plurality of prescribed addresses by said storage unit accessing device and said data of said received data packet.

Claim 21

The memory interface apparatus according to claim 18, wherein the storage unit address modifying device controls whether said address of said received data packet is modified based on said plurality of offsets or said data of said received data packet.

Claim 24

The method of claim 20, further comprising controlling whether said address of said received data packet is modified based on said plurality of offsets or said data of said received data packet.