US5860101A
Expired / Lapsed
US
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Scalable symmetric multiprocessor data-processing system with data allocation among private caches and segments of system memory
Assignee: International Business Machines Corp
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Filing: 1997-12-17
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Granted: 1999-01-12
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Expires: 2017-12-17
Abstract
Abstract A scalable symmetric multiprocessor data-processing system is disclosed. The symmetric multiprocessor data-processing system includes multiple processing units and a system memory. Each of the processing units includes a cache memory for storing a subset of data contained within the system memory. A cache controller is included within each one of the processing units for controlling an associated cache memory. The cache controller contains a mode select to allow an associated cache memory to be selectively operated under either a first mode or a second mode. Furthermore, the symmetric multiprocessor data-processing system also includes a multiple of partial system memories, wherein each of the partial system memories is associated with one of the processing units such that an aggregate of contents within all of the partial system memories forms the system memory.
Inventors
- 👤 Ravi Kumar Arimilli
- 👤 John Steven Dodson
- 👤 Jerry Don Lewis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:45
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0813; G06F2212/00; G06F2212/25; G06F2212/254; G06F2212/2542
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
154 words
A scalable symmetric multiprocessor data-processing system having a system memory, said data-processing system comprising: a plurality of processing units, wherein each of said plurality of processing units includes a cache memory for storing a subset of data contained within said system memory; a cache controller included within each one of said processing units for controlling an associated one of said cache memories, wherein said cache controller includes a mode select to allow an associated cache memory to be selectively operated under either a first mode or a second mode for indicating an address space of said system memory in which one of said cache memories can store data; and a plurality of partial system memories, wherein each of said plurality of partial system memories is associated with a respective one of said plurality of processing units, wherein an aggregate of contents within all of said plurality of partial system memories forms said system memory.
Claim 2
Dependent Claim
154 words
A scalable symmetric multiprocessor data-processing system having a system memory, said data-processing system comprising: a plurality of processing units, wherein each of said plurality of processing units includes a cache memory for storing a subset of data contained within said system memory; a cache controller included within each one of said processing units for controlling an associated one of said cache memories, wherein said cache controller includes a mode select to allow an associated cache memory to be selectively operated under either a first mode or a second mode for indicating an address space of said system memory in which one of said cache memories can store data; and a plurality of partial system memories, wherein each of said plurality of partial system memories is associated with a respective one of said plurality of processing units, wherein an aggregate of contents within all of said plurality of partial system memories forms said system memory.
Claim 3
Dependent Claim
31 words
The scalable symmetric multiprocessor data-processing system according to claim 1, wherein said first mode enables all of said cache memories combined to represent an entire address space of said system memory.
Claim 4
Dependent Claim
30 words
The scalable symmetric multiprocessor data-processing system according to claim 1, wherein said second mode enables each of said cache memories to represent an entire address space of said system memory.
Claim 5
Dependent Claim
22 words
The scalable symmetric multiprocessor data-processing system according to claim 1, wherein said plurality of processing units are substantially identical to each other.
Claim 6
Dependent Claim
33 words
The scalable symmetric multiprocessor data-processing system according to claim 1, wherein each of said plurality of partial system memories is associated with one of said plurality of processing units via a memory controller.
References Cited (Backward Citations)
US4646237A
Cited
US4881164A
Cited
US4755930A
Cited
US5329630A
Cited
US4969122A
Cited
US5247648A
Cited
US5353430A
Cited
US5303362A
Cited
US5684993A
Cited
US5604882A
Cited
US5694567A
Cited
US5664152A
Cited
US5680571A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |