Modular switch element for shared memory switch fabric

Claim 2

A modular switch element for shared memory switch fabric, comprising: a plurality of input ports; a plurality of output ports; a memory array coupled to the plurality of input ports and to the plurality of output ports; and a control logic unit coupled to the plurality of input ports, to the plurality of output ports, and to the memory array, the control logic receiving a size signal representative of a number of modular switch elements in a shared memory switch fabric, the control logic unit writing data input to the plurality of input ports into the memory array responsive to a first set of control signals and the size signal, and the control logic reading data stored in the memory array to the plurality of output ports responsive to a second set of control signals and the size signal, wherein one of the first set of control signals indicates a beginning of a data cell.

Claim 3

The modular switch element of claim 1 wherein the first and second set of control signals are generated by an input address register file and an output address register file, respectively.

Claim 4

The modular switch element of claim 1 further comprising a cell identifier bus, wherein the cell identifier bus outputs a predetermined portion of each data cell.

Claim 5

A modular switch element for shared memory switch fabric, comprising: a plurality of input ports; a plurality of output ports; a memory array coupled to the plurality of input ports and to the plurality of output ports; and a control logic unit coupled to the plurality of input ports, to the plurality of output ports, and to the memory array, the control logic receiving a size signal representative of a number of modular switch elements in a shared memory switch fabric, the control logic unit writing data input to the plurality of input ports into the memory array responsive to a first set of control signals and the size signal, and the control logic reading data stored in the memory array to the plurality of output ports responsive to a second set of control signals and the size signal; and a plurality of input shift-registers and a plurality of output shift-registers coupled to the plurality of input ports and to the plurality of output ports, respectively.

Claim 6

A modular switch element for shared memory switch fabric, comprising: a plurality of input ports; a plurality of output ports; a memory array coupled to the plurality of input ports and to the plurality of output ports; and a control logic unit coupled to the plurality of input ports, to the plurality of output ports, and to the memory array, the control logic receiving a size signal representative of a number of modular switch elements in a shared memory switch fabric, the control logic unit writing data input to the plurality of input ports into the memory array responsive to a first set of control signals and the size signal, and the control logic reading data stored in the memory array to the plurality of output ports responsive to a second set of control signals and the size signal; and a plurality of input shift-registers and a plurality of output shift-registers coupled to the plurality of input ports and to the plurality of output ports, respectively.

Claim 7

The modular switch element of claim 4, wherein the first and second set of control signals are generated by an input address register file and an output address register file, respectively.

Claim 8

The modular switch element of claim 4 further comprising a cell identifier bus, wherein the cell identifier bus outputs a predetermined portion of each data cell.

Claim 9

A modular switch element for shared memory switch fabric, comprising: N M-bit input shift-registers, where N and M are a non-zero integers; N input registers coupled to the N M-bit input shift-registers; a memory array coupled to the N input registers; N output registers coupled to the memory array; N M-bit output shift-registers coupled to the N output registers; N input address registers; N output address registers; and control logic coupled to the N M-bit input shift-registers, to the N input registers, to the memory array, to the N output registers, to the N M-bit output shift-registers, to the N input address registers, and to the N output address registers, wherein each the N M-bit input shift-registers serially receives a data cell and outputs an M-bit datum to one of the N input registers, where the control logic writes each M-bit datum to a differing location in the memory array, the location determined responsive to a differing one to the N input address registers and to a start frame signal, where the control logic reads a differing location in the memory array to a differing one of the N output registers responsive to the N output address registers, and where the N M-bit output shift-registers receive in parallel N M-bit data cells from the N output registers and serially output the N M-bit data cells.

Claim 10

A modular switch element for shared memory switch fabric, comprising: N M-bit input shift-registers, where N and M are a non-zero integers; N input registers coupled to the N M-bit input shift-registers; a memory array coupled to the N input registers; N output registers coupled to the memory array; N M-bit output shift-registers coupled to the N output registers; N input address registers; N output address registers; and control logic coupled to the N M-bit input shift-registers, to the N input registers, to the memory array, to the N output registers, to the N M-bit output shift-registers, to the N input address registers, and to the N output address registers, wherein each the N M-bit input shift-registers serially receives a data cell and outputs an M-bit datum to one of the N input registers, where the control logic writes each M-bit datum to a differing location in the memory array, the location determined responsive to a differing one to the N input address registers and to a start frame signal, where the control logic reads a differing location in the memory array to a differing one of the N output registers responsive to the N output address registers, and where the N M-bit output shift-registers receive in parallel N M-bit data cells from the N output registers and serially output the N M-bit data cells.

Claim 11

The modular switch element of claim 7 further comprising a cell identifier bus, wherein the cell identifier bus outputs a predetermined portion of each data cell.

Claim 12

The modular switch element of claim 7 wherein a plurality of the N M-bit output shift-registers simultaneously begins outputting a plurality of the N data cells.

Claim 13

The modular switch element of claim 7 wherein the control logic invalidates each one of the N input address registers after receiving the start frame signal.

Claim 14

The modular switch element of claim 7 wherein the control logic further comprises a counter, wherein an output of the counter is incremented with each M-bit datum, wherein a portion of the output of the counter is concatenated to each one of the N input address registers, the portion being responsive to an input size signal, and wherein each one of the N input address registers and each one of the N output address registers is invalidated upon an occurrence of a predetermined pattern in the counter.

Claim 15

A shared memory switch fabric for routing data cells between I inputs and O outputs, each data cell comprising B bits, where I, O, and B are non-zero integers, the shared memory switch fabric comprising: E modular switch elements, where E is a non-zero integer, wherein a Jth one of the E modular switch elements further comprises, where J is an integer index ranging from 0 to (E-1): I input ports coupled to receive the Jth bit of each of the I inputs; a memory array coupled to the I input ports; O output ports coupled to the memory array to output the Jth bit of each of the O outputs; control logic coupled to the I input ports, to the memory array and to the O output ports, the control logic writing data input to the I input ports into the memory array responsive to a first set of control signals and the control logic reading data stored in the memory array to the O output ports responsive to a second set of control signals; and a controller coupled to each of the E modular switch elements, the controller generating the first and second set of control signals.

Claim 16

A shared memory switch fabric for routing data cells between I inputs and O outputs, each data cell comprising B bits, where I, O, and B are non-zero integers, the shared memory switch fabric comprising: E modular switch elements, where E is a non-zero integer, wherein a Jth one of the E modular switch elements further comprises, where J is an integer index ranging from 0 to (E-1): I input ports coupled to receive the Jth bit of each of the I inputs; a memory array coupled to the I input ports; O output ports coupled to the memory array to output the Jth bit of each of the O outputs; control logic coupled to the I input ports, to the memory array and to the O output ports, the control logic writing data input to the I input ports into the memory array responsive to a first set of control signals and the control logic reading data stored in the memory array to the O output ports responsive to a second set of control signals; and a controller coupled to each of the E modular switch elements, the controller generating the first and second set of control signals.

Claim 17

The shared memory switch fabric of claim 12 wherein the control logic writes data input to the I input ports into the memory array responsive to the first set of control signals and to a size signal, and wherein the control logic reads data stored in the memory array to the O output ports responsive to the second set of control signals and to the size signal.

Claim 18

The shared memory switch fabric of claim 12 wherein one of the first set of control signals indicates a beginning of a data cell.

Claim 19

The shared memory switch fabric of claim 12 wherein each of the E modular switch elements further comprises an input address register file and an output address, and wherein the first and second set of control signals are generated by the input address register file and the output address register file, respectively.

Claim 20

The shared memory switch fabric of claim 12 wherein each of the E modular switch elements further comprises I input shift-registers and O output shift-registers coupled to the I input ports and to the O output ports, respectively.

Claim 21

The shared memory switch fabric of claim 16 wherein a plurality of the O output shift-registers simultaneously begin outputting a plurality of O data cells.

Claim 22

The shared memory switch fabric of claim 12 further comprising a cell identifier bus, wherein the cell identifier bus outputs a predetermined portion of each data cell to the controller.