Multi-level memory circuits and corresponding reading and writing methods

Claim 2

A memory circuit comprising: a plurality of memory elements, each capable of storing a multiplicity of binary information units, said plurality of memory elements having at least first and second modes of operation, the memory elements being utilized in said first mode of operation as if adapted for storing each a first number of binary information units, and being utilized in said second mode of operation as if adapted for storing each a second number of binary information units, said first and second numbers being dissimilar, said numbers chosen to have at least a two-level and multi-level mode of operation, at least two input/output terminals; a multiplexer connected to said input/output terminals; and a control unit connected to said multiplexer and operative to enable said modes of operation in relation to incoming selection instructions, wherein data in one mode can be obtained from data in the other mode.

Claim 3

A memory circuit according to claim 1, wherein said first number is one and said second number is two.

Claim 4

A memory circuit according to claim 1, wherein said plurality of memory elements are substantially identical, arranged into a matrix, and accessed through a common access circuit.

Claim 5

A memory circuit according to claim 1, wherein said control unit has control inputs and is operative to enable said modes of operation in relation to electric control signals to said control inputs concurrently with at least one of reading and writing operations.

Claim 6

A memory circuit according to claim 1, wherein said control unit has control inputs and is operative to enable said modes of operation in relation to electric control signals to said control inputs in advance of at least one of reading and writing operations.

Claim 7

A memory circuit according to claim 1, wherein said control unit is operative to define at least one of said first and second numbers in relation to said incoming selection instructions.

Claim 8

A memory circuit comprising: a plurality of memory elements divided into at least a first set and a second set, memory elements in said first set being utilized in a first mode of operation as if adapted for storing each a first number of binary information units, and memory elements in said second set being utilized in a second mode of operation as if adapted for storing each a second number of binary information units, said first and second numbers being dissimilar, said numbers chosen to have at least a two-level and multi-level mode of operation, at least two input/output terminals; a multiplexer connected to said input/output terminals; and a control unit connected to said multiplexer and operative to enable said modes of operation in relation to incoming selection instructions, wherein data in one mode can be obtained from data in the other mode.

Claim 9

A memory circuit comprising: a plurality of memory elements divided into at least a first set and a second set, memory elements in said first set being utilized in a first mode of operation as if adapted for storing each a first number of binary information units, and memory elements in said second set being utilized in a second mode of operation as if adapted for storing each a second number of binary information units, said first and second numbers being dissimilar, said numbers chosen to have at least a two-level and multi-level mode of operation, at least two input/output terminals; a multiplexer connected to said input/output terminals; and a control unit connected to said multiplexer and operative to enable said modes of operation in relation to incoming selection instructions, wherein data in one mode can be obtained from data in the other mode.

Claim 10

A memory circuit according to claim 7, wherein said first number is one and said second number is two.

Claim 11

A memory circuit according to claim 7, wherein said plurality of memory elements are substantially identical, arranged into a matrix, and accessed through a common access circuit.

Claim 12

A memory circuit according to claim 7, wherein said control unit is operative to define at least one of said first and second sets in relation to incoming definition instructions.

Claim 13

A memory circuit according to claim 7, wherein said control unit is operative to enable said first mode of operation when a memory element in said first set is addressed, and to enable said second mode of operation when a memory element in said second set is addressed.

Claim 14

A memory circuit according to claim 7, wherein said control unit is operative to define at least one of said first and second numbers in relation to incoming definition instructions.

Claim 15

A semiconductor integrated electronic storage device comprising: at least one memory circuit, said at least one memory circuit comprising a plurality of memory elements, each capable of storing a multiplicity of binary information units, said plurality of memory elements having at least first and second modes of operation, the memory elements being utilized in said first mode of operation as if adapted for storing each a first number of binary information units, and being utilized in said second mode of operation as if adapted for storing each a second number of binary information units, said first and second numbers being dissimilar, said numbers chosen to have at least a two-level and multi-level mode of operation, at least two input/output terminals; a multiplexer connected to said input/output terminals; and a control unit connected to said multiplexer and operative to enable said modes of operation in relation to incoming selection instructions, wherein data in one mode can be obtained from data in the other mode.

Claim 16

A semiconductor integrated electronic storage device comprising: at least one memory circuit, said at least one memory circuit comprising a plurality of memory elements, each capable of storing a multiplicity of binary information units, said plurality of memory elements having at least first and second modes of operation, the memory elements being utilized in said first mode of operation as if adapted for storing each a first number of binary information units, and being utilized in said second mode of operation as if adapted for storing each a second number of binary information units, said first and second numbers being dissimilar, said numbers chosen to have at least a two-level and multi-level mode of operation, at least two input/output terminals; a multiplexer connected to said input/output terminals; and a control unit connected to said multiplexer and operative to enable said modes of operation in relation to incoming selection instructions, wherein data in one mode can be obtained from data in the other mode.

Claim 17

A device according to claim 13, further comprising a logic circuit connected to said at least one memory circuit for at least one of reading information therefrom and writing information thereto.

Claim 18

A device according to claim 13, wherein said first number is one and said second number is two.

Claim 19

A device according to claim 13, wherein said plurality of memory elements are substantially identical, arranged into a matrix, and accessed through a common access circuit.

Claim 20

A device according to claim 13, wherein said control unit has control inputs and is operative to enable said modes of operation in relation to electric control signals to said control inputs concurrently with at least one of reading and writing operations.

Claim 21

A device according to claim 13, wherein said control unit has control inputs and is operative to enable said modes of operation in relation to electric control signals to said control inputs in advance of at least one of reading and writing operations.

Claim 22

A device according to claim 13, wherein said control unit is operative to define at least one of said first and second numbers in relation to incoming definition instructions.