US5858814A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hybrid chip and method therefor
Assignee: Avago Technologies International Sales Pte Ltd
•
Filing: 1996-12-12
•
Granted: 1999-01-12
•
Expires: 2016-12-12
Abstract
Abstract A hybrid chip having at least two different types of semiconductor devices co-located on a common substrate, and a method therefor, are disclosed. The devices have different multiple epitaxial layer structures so that each different type of device is first grown on a separate appropriately-selected substrate, and then attached to the common substrate. According to the method, a first device is attached to the common substrate using flip-chip bonding methods. Flip-chip bonding involves attaching the device and the substrate at bonding pads, flowing a flowable hardener between the first device and the common substrate and allowing it to harden, and then removing the substrate upon which the first device was grown. The hardener is removed before attaching the second type of device via flip-chip bonding.
Inventors
- 👤 Keith Wayne Goossen
- 👤 James A. Walker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:06
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/70; H10P72/74; H10W; H10W90/00; H10P72/743; H10P72/7432; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
251 words
A method for co-locating, on a common semiconductor substrate, first and second devices having different multiple epitaxial layer structures, comprising the steps of depositing a first stop-etch layer on a first substrate, forming the first device at a first location on the first stop-etch layer, and removing said first stop-etch layer from the first substrate at locations other than the first location, wherein, the first device comprises a first contact pad located distal to the first stop-etch layer; depositing a second stop-etch layer on a second substrate, forming the second device at a second location on the second stop-etch layer and removing said second stop-etch layer from the second substrate at locations other than the second location wherein, the second device comprises a second contact pad located distal to the second stop-etch layer; bonding the first device to the common semiconductor substrate such that, relative to said first stop-etch layer, the first contact pad is proximal to said common semiconductor substrate; flowing a flowable hardener around the first device; removing the first substrate; removing the flowable hardener; bonding the second device to the common semiconductor substrate such that, relative to said second stop-etch layer, the second contact pad is proximal to said common semiconductor substrate, and, relative to the second stop-etch layer, the first stop-etch layer is relatively nearer to the common semiconductor substrate so that a gap is defined between the first stop-etch layer and the second substrate; and flowing the flowable hardener around the first and the second device.
Claim 2
Independent Claim
251 words
A method for co-locating, on a common semiconductor substrate, first and second devices having different multiple epitaxial layer structures, comprising the steps of depositing a first stop-etch layer on a first substrate, forming the first device at a first location on the first stop-etch layer, and removing said first stop-etch layer from the first substrate at locations other than the first location, wherein, the first device comprises a first contact pad located distal to the first stop-etch layer; depositing a second stop-etch layer on a second substrate, forming the second device at a second location on the second stop-etch layer and removing said second stop-etch layer from the second substrate at locations other than the second location wherein, the second device comprises a second contact pad located distal to the second stop-etch layer; bonding the first device to the common semiconductor substrate such that, relative to said first stop-etch layer, the first contact pad is proximal to said common semiconductor substrate; flowing a flowable hardener around the first device; removing the first substrate; removing the flowable hardener; bonding the second device to the common semiconductor substrate such that, relative to said second stop-etch layer, the second contact pad is proximal to said common semiconductor substrate, and, relative to the second stop-etch layer, the first stop-etch layer is relatively nearer to the common semiconductor substrate so that a gap is defined between the first stop-etch layer and the second substrate; and flowing the flowable hardener around the first and the second device.
Claim 3
Dependent Claim
14 words
The method of claim 1 further comprising the step of removing the second substrate.
Claim 4
Dependent Claim
15 words
The method of claim 1 further comprising the step of removing the second stop-etch layer.
Claim 5
Dependent Claim
20 words
The method of claim 1 further comprising removing the flowable hardener that was flowed around the first and second devices.
Claim 6
Dependent Claim
33 words
The method of claim 1 wherein the first and the second device are individually selected from the group consisting of gallium arsenide-based devices and indium phosphide-based devices and the common substrate is silicon.
Claim 7
Dependent Claim
22 words
The method of claim 1 wherein at least one of the first and the second devices comprise a III-V compound semiconductor layer.
Claim 8
Independent Claim
175 words
A method for attaching a surface emitting laser and a p-i-n diode to a silicon electronics chip, comprising the steps of: depositing a first stop-etch layer on a first substrate, forming the p-i-n diode at a first location on the first stop-etch layer and removing said first stop-etch layer from the first substrate at locations other than the first location; depositing a second stop-etch layer on a second substrate, forming the surface emitting laser at a second location on the second stop-etch layer and removing said second stop-etch layer from the second substrate at locations other than the second location; bonding the p-i-n diode on the first substrate to the silicon electronics chip; flowing a flowable hardener around the p-i-n diode; removing the first substrate; removing the flowable hardener; bonding the surface emitting laser on the second substrate to the silicon electronics chip, wherein, there is a gap between the first stop-etch layer on the p-i-n diode and the second substrate; and flowing a flowable hardener around the surface emitting laser and the p-i-n diode.
Claim 9
Independent Claim
175 words
A method for attaching a surface emitting laser and a p-i-n diode to a silicon electronics chip, comprising the steps of: depositing a first stop-etch layer on a first substrate, forming the p-i-n diode at a first location on the first stop-etch layer and removing said first stop-etch layer from the first substrate at locations other than the first location; depositing a second stop-etch layer on a second substrate, forming the surface emitting laser at a second location on the second stop-etch layer and removing said second stop-etch layer from the second substrate at locations other than the second location; bonding the p-i-n diode on the first substrate to the silicon electronics chip; flowing a flowable hardener around the p-i-n diode; removing the first substrate; removing the flowable hardener; bonding the surface emitting laser on the second substrate to the silicon electronics chip, wherein, there is a gap between the first stop-etch layer on the p-i-n diode and the second substrate; and flowing a flowable hardener around the surface emitting laser and the p-i-n diode.
Claim 10
Dependent Claim
14 words
The method of claim 7 further comprising the step of: removing the second substrate.
Claim 11
Dependent Claim
20 words
The method of claim 8 further comprising the step of removing the second stop-etch layer from the surface emitting laser.
Claim 12
Dependent Claim
16 words
The method of claim 7 wherein the p-i-n diode functions as a multiple quantum well modulator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |