US5856823A
Expired / Lapsed
US
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Plasma display
Assignee: Panasonic Holdings Corp
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Filing: 1995-09-14
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Granted: 1999-01-05
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Expires: 2015-09-14
Abstract
Abstract A plasma display having a quartet type pixel structure provides a high grade and excellent picture quality picture and maintains good white balance and excellent intensity levels. The plasma display comprises a reference circuit φ for outputting a control signal based on the least significant bit of a digitized green video signal and a timing signal and an arithmetic circuit 8 for performing an arithmetic operation on the output of the reference circuit. As a result of this arrangement, the least significant bit information, that was lost by halving the green signal value to maintain the white balance is incorporated in the halved green signal based on a timing signal, thereby realizing 256 intensity levels without degrading the halftone in the video picture.
Inventors
- 👤 Takayuki Kimoto
- 👤 Isao Kawahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:24
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/22; G09G3/28; G09G3/282; G09G2300/00; G09G2300/04; G09G2300/0439; G09G2300/0452; G09G2320/00; G09G2320/06; G09G2320/0666; G09G3/2007; G09G3/2074; Y; Y10; Y10T; Y10T428/00; Y10T428/12; Y10T428/12354; Y10T428/12375
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
87 words
A plasma display including a plurality of pixel units, each pixel unit including two green pixels, one blue pixel and one red pixel, the plasma display comprising: a reference circuit for outputting a control signal based on the least significant bit of a digitized green video signal and a timing signal; an arithmetic circuit for performing an arithmetic operation on said digitized green video signal and control signal; and a driving circuit for receiving digitized red and blue signals together with the output from said arithmetic circuit.
Claim 2
Dependent Claim
87 words
A plasma display including a plurality of pixel units, each pixel unit including two green pixels, one blue pixel and one red pixel, the plasma display comprising: a reference circuit for outputting a control signal based on the least significant bit of a digitized green video signal and a timing signal; an arithmetic circuit for performing an arithmetic operation on said digitized green video signal and control signal; and a driving circuit for receiving digitized red and blue signals together with the output from said arithmetic circuit.
Claim 3
Dependent Claim
50 words
The plasma display according to claim 1, wherein the control signal from the reference circuit is a logical product between the least significant bit of the digitized green video signal and a signal obtained by dividing by two a sampling clock used to digitize the red, blue, and green signals.
Claim 4
Dependent Claim
68 words
The plasma display according to claim 1, wherein the control signal from the reference circuit is a logical product between, (a) an exclusive OR of a signal obtained by dividing by two a sampling clock used to digitize the red, blue and green signals and a signal obtained by dividing by two a horizontal synchronizing signal, and (b) the least significant bit of the digitized green video signal.
Claim 5
Dependent Claim
42 words
The plasma display according to claim 1, wherein the arithmetic circuit is an addition circuit for adding 1 to the digitized video signal of one of the two green pixels selected according to the least significant bit of the digitized green signal.
Claim 6
Dependent Claim
42 words
The plasma display according to claim 1, wherein the arithmetic circuit is a subtraction circuit for subtracting 1 from the digitized video signal of one of the two green pixels selected according to the least significant bit of the digitized green signal.
References Cited (Backward Citations)
GB1494509A
Cited
US5341153A
Cited
JPH04195087A
Cited
US5170152A
Cited
US5479189A
Cited
EP0525750A2
Cited
US5469190A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-04 | 2002-07-06 | 2003-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-04 | 2006-07-06 | 2007-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-04 | 2010-07-06 | 2011-01-05 | $7700.00 | Window Closed / Lapsed |