US5854121A
Expired / Lapsed
US
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Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure
Assignee: GlobalFoundries Inc
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Filing: 1997-09-04
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Granted: 1998-12-29
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Expires: 2017-09-04
Abstract
Abstract A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. The semiconductor topography is then exposed to a barrier-entrained gas and heated so that barrier atoms become incorporated in regions of the active areas in close proximity to the trench isolation structure. The masking layer may prevent the barrier atoms from being incorporated into any other regions of the substrate.
Inventors
- 👤 Mark I. Gardner
- 👤 H. Jim Fulford
- 👤 Derick J. Wristers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:46
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6322; H10P14/65; H10P14/6516; H10P14/6518; H10P14/6524; H10P14/6526; H10P14/6529; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
125 words
A method for forming a trench isolation region, comprising: providing a semiconductor topography comprising a masking layer disposed above a semiconductor substrate, wherein an opening is formed vertically through said masking layer; forming first and second dielectric spacers laterally adjacent to opposed sidewall surfaces of said opening; etching a trench within said substrate between said first and second dielectric spacers; forming dielectric material within said trench and said opening; removing portions of said dielectric material and said first and second dielectric spacers such that an upper surface of said dielectric material is approximately commensurate with an upper surface of said substrate; and incorporating barrier atoms in areas of said substrate directly beneath said first and second spacers and laterally adjacent to sidewalls of said trench.
Claim 2
Independent Claim
125 words
A method for forming a trench isolation region, comprising: providing a semiconductor topography comprising a masking layer disposed above a semiconductor substrate, wherein an opening is formed vertically through said masking layer; forming first and second dielectric spacers laterally adjacent to opposed sidewall surfaces of said opening; etching a trench within said substrate between said first and second dielectric spacers; forming dielectric material within said trench and said opening; removing portions of said dielectric material and said first and second dielectric spacers such that an upper surface of said dielectric material is approximately commensurate with an upper surface of said substrate; and incorporating barrier atoms in areas of said substrate directly beneath said first and second spacers and laterally adjacent to sidewalls of said trench.
Claim 3
Dependent Claim
33 words
The method of claim 1, wherein said semiconductor topography further comprises an oxide layer interposed between said semiconductor substrate and said masking layer, and wherein said opening extends partially through said oxide layer.
Claim 4
Dependent Claim
12 words
The method of claim 1, wherein said masking layer comprises silicon nitride.
Claim 5
Dependent Claim
58 words
The method of claim 1, wherein the step of forming said first and second dielectric spacers comprises: depositing an insulative layer across exposed surfaces of said masking layer and said opening; etching said insulative layer at a greater rate perpendicular to said semiconductor substrate than parallel to said semiconductor substrate to form said first and second dielectric spacers.
Claim 6
Dependent Claim
22 words
The method of claim 4, wherein said insulative layer comprises a material selected from the group consisting of oxide, nitride, and oxynitride.
Claim 7
Dependent Claim
35 words
The method of claim 1, further comprising implanting dopants into an exposed region of said substrate directly under said trench prior to the step of forming said dielectric material in said trench and said opening.
Claim 8
Dependent Claim
69 words
The method of claim 1, wherein the step of forming said dielectric material in said trench and said opening comprises: thermally growing an oxide layer in said trench on exposed regions of said semiconductor substrate; depositing a fill oxide across said masking layer and into said opening and said trench; and chemical-mechanical polishing said fill oxide to an elevational level directly below an upper surface of said masking layer.
Claim 9
Dependent Claim
21 words
The method of claim 1, wherein each of said first and second dielectric spacers has a width of about 0.1 micron.
Claim 10
Dependent Claim
66 words
The method of claim 1, wherein the step of removing said portions of said dielectric material and said first and second spacers comprises (i) forming a photoresist layer exclusively above said masking layer and (ii) plasma etching or wet etching said portions of said dielectric material and said first and second spacers such that said first and second spacers are about 0 to 200 Å thick.
Claim 11
Dependent Claim
12 words
The method of claim 1, wherein said barrier atoms comprises nitrogen atoms.
Claim 12
Dependent Claim
43 words
The method of claim 10, wherein the step of incorporating said barrier atoms comprises heating said semiconductor topography in a nitrogen-bearing ambient such that said nitrogen atoms are forwarded into said areas of said substrate where they form bonds with available silicon atoms.
Claim 13
Dependent Claim
27 words
The method of claim 1, further comprising removing said first and second nitride spacers and said masking layer, subsequent to the step of incorporating said barrier atoms.
Claim 14
Dependent Claim
20 words
The method of claim 1, wherein said areas of said substrate are portions of active regions of said semiconductor substrate.
References Cited (Backward Citations)
US5545290A
Cited
US5506168A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-28 | 2002-06-29 | 2002-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-28 | 2006-06-29 | 2006-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-28 | 2010-06-29 | 2010-12-29 | $7700.00 | Window Closed / Lapsed |