US5848367A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for sharing a non-volatile memory element as a boot device
Assignee: Sony Corp
•
Filing: 1996-09-13
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Granted: 1998-12-08
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Expires: 2016-09-13
Abstract
Abstract A system and method for multiple processors operating independently from one another to share memory as a boot device. The system includes a plurality of computing systems each including a processor and a local memory element. In response to a boot condition for a selected computing system, its processor begins a boot sequence in which it uses operational code contained within a non-volatile memory element that is shared by each of the computing systems. Arbitration for ownership of a memory bus interconnecting the non-volatile memory element to the processors and organization of a direct memory access transfer between the non-volatile memory element and local memory associated with the processor of the selected computing system is controlled by a memory access coordination circuit coupled between the computing systems and the memory bus.
Inventors
- 👤 Daniel A. Lotocky
- 👤 Michael R. Atkinson
- 👤 Troy D. Batterberry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:07
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1417
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
224 words
A digital entertainment system implemented within a vehicle having at least one peripheral device associated with individual passenger seats within the vehicle, the digital entertainment system comprising: a headend control system to transmit information in a first digital format; a bridge circuit coupled to said headend control system, said bridge circuit to receive the information in the first digital format, to convert the information into a second digital format, and to output the information in the second digital format; and a plurality of seat electronics units coupled to the bridge circuit, each of said plurality of seat electronics units including a memory bus, a non-volatile memory element coupled to the memory bus, said non-volatile memory element contains operational code used during a boot sequence, a plurality of computing systems uniquely controlling operations of at least one peripheral device associated with a passenger seat, each computer system including a processor and a local memory element, to perform the boot sequence in response to a boot condition, and a memory access coordination circuit coupled to the memory bus and to each of the plurality of computing systems, said memory access coordination circuit to control arbitration of the memory bus and to control a direct memory access transfer of the operational code from the non-volatile memory element to the local memory element associated with the selected processor.
Claim 2
Dependent Claim
224 words
A digital entertainment system implemented within a vehicle having at least one peripheral device associated with individual passenger seats within the vehicle, the digital entertainment system comprising: a headend control system to transmit information in a first digital format; a bridge circuit coupled to said headend control system, said bridge circuit to receive the information in the first digital format, to convert the information into a second digital format, and to output the information in the second digital format; and a plurality of seat electronics units coupled to the bridge circuit, each of said plurality of seat electronics units including a memory bus, a non-volatile memory element coupled to the memory bus, said non-volatile memory element contains operational code used during a boot sequence, a plurality of computing systems uniquely controlling operations of at least one peripheral device associated with a passenger seat, each computer system including a processor and a local memory element, to perform the boot sequence in response to a boot condition, and a memory access coordination circuit coupled to the memory bus and to each of the plurality of computing systems, said memory access coordination circuit to control arbitration of the memory bus and to control a direct memory access transfer of the operational code from the non-volatile memory element to the local memory element associated with the selected processor.
Claim 3
Dependent Claim
16 words
The digital entertainment system according to claim 1, wherein the non-volatile memory element includes flash memory.
Claim 4
Dependent Claim
26 words
The digital entertainment system according to claim 1, wherein the memory access coordination circuit includes a micro-controller to control set-up of the direct memory access transfer.
Claim 5
Dependent Claim
39 words
The digital entertainment system according to claim 3, wherein the memory access coordination circuit further includes a storage element coupled to the micro-controller, said storage element contains code executed by the micro-controller to set-up the direct memory access transfer.
Claim 6
Dependent Claim
29 words
The digital entertainment system according to claim 4, wherein the storage element of the memory access coordination circuit further contains information pertaining to a seat configuration of the vehicle.
Claim 7
Dependent Claim
88 words
The digital entertainment system according to claim 3, wherein the memory access coordination circuit further including: a first bus; a second bus coupled to the micro-controller; a first bus interface unit coupled to both the plurality of computing systems and the first bus; a plurality of message buffers coupled to the first bus; a plurality of pre-fetch buffers coupled to the first bus; a plurality of control registers coupled to the first bus; and a second bus interface unit coupled to the first bus and the second bus.
Claim 8
Dependent Claim
53 words
The digital entertainment system according to claim 6, wherein the plurality of message buffers of the memory access coordination circuit includes a send message buffer and a receive message buffer dedicated to each of the plurality of computing systems, said plurality of message buffers control communications between the selected processor and the micro-controller.
Claim 9
Dependent Claim
39 words
The digital entertainment system according to claim 7, wherein the plurality of pre-fetch buffers of the memory access coordination circuit are used to reduce loading on the second bus by supporting data bursts during the direct memory access transfer.
Claim 10
Dependent Claim
33 words
The digital entertainment system according to claim 8, wherein the plurality of control registers of the memory access coordination circuit are used to contain parameters needed to perform the direct memory access transfer.
Claim 11
Dependent Claim
99 words
The digital entertainment system according to claim 1, wherein the memory access coordination circuit includes: a first bus; a first bus interface unit coupled to both the plurality of computing systems and the first bus; a plurality of pre-fetch buffers coupled to the first bus; a plurality of control registers coupled to the first bus; and a plurality of register sets coupled to the first bus, each of the register sets uniquely corresponding to one of the plurality of computing systems and including information needed by the plurality of control registers to set up the direct memory access transfer.
Claim 12
Dependent Claim
132 words
A circuit that controls propagation of data to at least one peripheral device placed within a vehicle, the circuit comprising: a memory bus; a non-volatile memory element coupled to the memory bus, said non-volatile memory element to contain operational code used during a boot sequence; a plurality of computing systems each including a processor and a local memory element, each of the plurality of computing systems to perform the boot sequence in response to a boot condition; and a memory access coordination circuit coupled to the memory bus and to the plurality of computing systems, said memory access coordination circuit to control a direct memory access transfer of the operational code from the non-volatile memory element to the local memory element associated with a selected processor of one of the computer systems.
Claim 13
Dependent Claim
132 words
A circuit that controls propagation of data to at least one peripheral device placed within a vehicle, the circuit comprising: a memory bus; a non-volatile memory element coupled to the memory bus, said non-volatile memory element to contain operational code used during a boot sequence; a plurality of computing systems each including a processor and a local memory element, each of the plurality of computing systems to perform the boot sequence in response to a boot condition; and a memory access coordination circuit coupled to the memory bus and to the plurality of computing systems, said memory access coordination circuit to control a direct memory access transfer of the operational code from the non-volatile memory element to the local memory element associated with a selected processor of one of the computer systems.
Claim 14
Dependent Claim
30 words
The circuit according to claim 11, wherein the memory access coordination circuit further controlling arbitration of the memory bus during the boot sequence to award ownership to the selected processor.
Claim 15
Dependent Claim
14 words
The circuit according to claim 11, wherein the non-volatile memory element includes flash memory.
Claim 16
Dependent Claim
24 words
The circuit according to claim 12, wherein the memory access coordination circuit includes a micro-controller to control set-up of the direct memory access transfer.
Claim 17
Dependent Claim
37 words
The circuit according to claim 14, wherein the memory access coordination circuit further includes a storage element coupled to the micro-controller, said storage element contains code executed by the micro-controller to set-up the direct memory access transfer.
Claim 18
Dependent Claim
27 words
The circuit according to claim 15, wherein the storage element of the memory access coordination circuit further contains information pertaining to a seat configuration of the vehicle.
Claim 19
Dependent Claim
86 words
The circuit according to claim 14, wherein the memory access coordination circuit further including: a first bus; a second bus coupled to the micro-controller; a first bus interface unit coupled to both the plurality of computing systems and the first bus; a plurality of message buffers coupled to the first bus; a plurality of pre-fetch buffers coupled to the first bus; a plurality of control registers coupled to the first bus; and a second bus interface unit coupled to the first bus and the second bus.
Claim 20
Dependent Claim
51 words
The circuit according to claim 17, wherein the plurality of message buffers of the memory access coordination circuit includes a send message buffer and a receive message buffer dedicated to each of the plurality of computing systems, said plurality of message buffers control communications between the selected processor and the micro-controller.
Claim 21
Dependent Claim
37 words
The circuit according to claim 18, wherein the plurality of pre-fetch buffers of the memory access coordination circuit are used to reduce loading on the second bus by supporting data bursts during the direct memory access transfer.
Claim 22
Dependent Claim
31 words
The circuit according to claim 19, wherein the plurality of control registers of the memory access coordination circuit are used to contain parameters needed to perform the direct memory access transfer.
Claim 23
Dependent Claim
97 words
The circuit according to claim 11, wherein the memory access coordination circuit includes: a first bus; a first bus interface unit coupled to both the plurality of computing systems and the first bus; a plurality of pre-fetch buffers coupled to the first bus; a plurality of control registers coupled to the first bus; and a plurality of register sets coupled to the first bus, each of the register sets uniquely corresponding to one of the plurality of computing systems and including information needed by the plurality of control registers to set up the direct memory access transfer.
Claim 24
Independent Claim
113 words
A method for performing a boot sequence by obtaining operational code from a memory element of which its contents are shared by a plurality of processors, the method comprising the steps of: determining that a boot condition exists in at least one processor of the plurality of processors; preparing for a direct memory access transfer from the memory element to a memory local to the at least one processor; requesting ownership of the memory bus for transferring operational code into the memory local to the at least one processor; and performing the direct memory access transfer of operational code from the memory element into the memory local to the at least one processor.
Claim 25
Independent Claim
113 words
A method for performing a boot sequence by obtaining operational code from a memory element of which its contents are shared by a plurality of processors, the method comprising the steps of: determining that a boot condition exists in at least one processor of the plurality of processors; preparing for a direct memory access transfer from the memory element to a memory local to the at least one processor; requesting ownership of the memory bus for transferring operational code into the memory local to the at least one processor; and performing the direct memory access transfer of operational code from the memory element into the memory local to the at least one processor.
Claim 26
Dependent Claim
20 words
The method of claim 22, wherein the performing step occurs after receiving a grant of ownership of the memory bus.
Claim 27
Dependent Claim
20 words
The method of claim 22, wherein the preparing step includes the steps of: providing a section index to a microcontroller.
Claim 28
Dependent Claim
57 words
The method of claim 24, wherein the providing step includes the steps of sending a pre-formatted message into a first buffer, the message includes the section index; interrupting the micro-controller to indicate the message is in the first buffer; and reading the message by the micro-controller to determine a starting address of the direct memory access transfer.
References Cited (Backward Citations)
US3795771A
Cited
US4428078A
Cited
US4352200A
Cited
US4774514A
Cited
US4584603A
Cited
US4647980A
Cited
US4647980B1
Cited
US4763360A
Cited
US4866515A
Cited
US4896209A
Cited
US4835604A
Cited
US4897714A
Cited
US4975696A
Cited
US4920432A
Cited
US5347632A
Cited
US5123015A
Cited
US5214505A
Cited
US5220419A
Cited
US5289272A
Cited
US5311302A
Cited
US5586937A
Cited
US5596647A
Cited
US5581270A
Cited
US5529265A
Cited
US5414455A
Cited
US5442390A
Cited
US5404567A
Cited
US5631693A
Cited
US5628027A
Cited
US5539448A
Cited
US5568181A
Cited
US5568180A
Cited
US5608447A
Cited
US5572442A
Cited
US5557541A
Cited
US5568614A
Cited
US5555466A
Cited
US5634012A
Cited
US5568484A
Cited
US5610822A
Cited
US5612730A
Cited
US5608448A
Cited
US5586121A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |