Amplifier circuit operating with single bias supply and less sensitive to fluctuation of threshold

Claim 2

An amplifier circuit operative to amplify an input signal for producing an output signal, comprising: a field effect transistor having a gate node supplied with said input signal from a signal input node, a source node for a source current and a drain node connected to a power voltage line for a drain current and supplying said output signal to a signal output node; a first resistive element connected between said source node and a constant voltage source for providing a resistance against said source current; and a gate bias circuit powered by said sower voltage line, and having a diode element for applying a gate bias voltage to said gate node, said diode element having a first node electrically connected to said source node and said gate electrode and a second node connected to said constant voltage source.

Claim 3

An amplifier circuit operative to amplify an input signal for producing an output signal, comprising: a field effect transistor having a gate node supplied with said input signal from a signal input node, a source node for a source current and a drain node connected to a power voltage line for a drain current and supplying said output signal to a signal output node; a first resistive element connected between said source node and a constant voltage source for providing a resistance against said source current; a gate bias circuit powered by said power voltage line, and having a diode element for applying a gate bias voltage to said gate node; a first capacitive element connected to said signal input node; a second capacitive element connected to said constant voltage source; an input matching circuit having a first node electrically connected to said first capacitive element, a second node electrically connected to said gate node and a third node electrically connected to said second capacitive element, said gate bias voltage being supplied from said gate bias circuit through said input matching circuit to said gate note; a third capacitive element connected to said signal output node; a fourth capacitive element connected to said constant voltage source; an output matching circuit having a first node electrically connected to said drain node, a second node electrically connected to said third capacitive element and a third node electrically connected to said fourth capacitive element, and said drain current being supplied from said power voltage line through said output matching circuit to said drain node; and a fifth capacitive element connected between said source node and said constant voltage source.

Claim 4

An amplifier circuit operative to amplify an input signal for producing an output signal, comprising: a field effect transistor having a gate node supplied with said input signal from a signal input node, a source node for a source current and a drain node connected to a power voltage line for a drain current and supplying said output signal to a signal output node; a first resistive element connected between said source node and a constant voltage source for providing a resistance against said source current; a gate bias circuit powered by said power voltage line, and having a diode element for applying a gate bias voltage to said gate node; a first capacitive element connected to said signal input node; a second capacitive element connected to said constant voltage source; an input matching circuit having a first node electrically connected to said first capacitive element, a second node electrically connected to said gate node and a third node electrically connected to said second capacitive element, said gate bias voltage being supplied from said gate bias circuit through said input matching circuit to said gate note; a third capacitive element connected to said signal output node; a fourth capacitive element connected to said constant voltage source; an output matching circuit having a first node electrically connected to said drain node, a second node electrically connected to said third capacitive element and a third node electrically connected to said fourth capacitive element, and said drain current being supplied from said power voltage line through said output matching circuit to said drain node; and a fifth capacitive element connected between said source node and said constant voltage source.

Claim 5

An amplifier circuit comprising: a depletion type field effect transistor having a gate node, a source node and a drain node; a first capacitive element connected to a signal input node to which an input signal is supplied; a second capacitive element connected to a constant voltage source; an input matching circuit having a first node connected to said first capacitive element, a second node connected to said gate node and a third node connected to said second capacitive element; a third capacitive element connected to a signal output node to which an output signal is supplied from said drain node; a fourth capacitive element connected to said constant voltage source; an output matching circuit having a first node connected to said third capacitive element, a second node connected to said drain node and a third node connected to said fourth capacitive element and a power supply line so as to transfer a drain current from said power voltage line to said drain node; a fifth capacitive element connected between said source node and said constant voltage source; a first resistive element connected between said source node and said constant voltage source; and a series of a second resistive element and a diode element connected between said power voltage line and said constant voltage source so as to supply a gate bias voltage from a node between said second resistive element and said diode element to said third node of said input matching circuit.

Claim 6

An amplifier circuit comprising: a depletion type field effect transistor having a gate node, a source node and a drain node; a first capacitive element connected to a signal input node to which an input signal is supplied; a second capacitive element connected to a constant voltage source; an input matching circuit having a first node connected to said first capacitive element, a second node connected to said gate node and a third node connected to said second capacitive element; a third capacitive element connected to a signal output node to which an output signal is supplied from said drain node; a fourth capacitive element connected to said constant voltage source; an output matching circuit having a first node connected to said third capacitive element, a second node connected to said drain node and a third node connected to said fourth capacitive element and a power supply line so as to transfer a drain current from said power voltage line to said drain node; a fifth capacitive element connected between said source node and said constant voltage source; a first resistive element connected between said source node and said constant voltage source; and a series of a second resistive element and a diode element connected between said power voltage line and said constant voltage source so as to supply a gate bias voltage from a node between said second resistive element and said diode element to said third node of said input matching circuit.

Claim 7

An amplifier circuit comprising: a depletion type field effect transistor having a gate node, a source node and a drain node; a first capacitive element connected to a signal input node to which an input signal is supplied; a second capacitive element connected to a constant voltage source; an input matching circuit having a first node connected to said first capacitive element, a second node connected to said gate node and a third node connected to said second capacitive element; a third capacitive element connected to a signal output node to which an output signal is supplied from said drain node; a fourth capacitive element connected to said constant voltage source; an output matching circuit having a first node connected to said third capacitive element, a second node connected to said drain node and a third node connected to said fourth capacitive element and a power supply line so as to transfer a drain current from said power voltage line to said drain node; a fifth capacitive element connected between said source node and said constant voltage source; a first resistive element connected between said source node and said constant voltage source; and a series of a second resistive element and a diode element connected between said source node and said constant voltage source so as to supply a gate bias voltage from a node between said second resistive element and said diode element to said third node of said input matching circuit.

Claim 8

An amplifier circuit comprising: a depletion type field effect transistor having a gate node, a source node and a drain node; a first capacitive element connected to a signal input node to which an input signal is supplied; a second capacitive element connected to a constant voltage source; an input matching circuit having a first node connected to said first capacitive element, a second node connected to said gate node and a third node connected to said second capacitive element; a third capacitive element connected to a signal output node to which an output signal is supplied from said drain node; a fourth capacitive element connected to said constant voltage source; an output matching circuit having a first node connected to said third capacitive element, a second node connected to said drain node and a third node connected to said fourth capacitive element and a power supply line so as to transfer a drain current from said power voltage line to said drain node; a fifth capacitive element connected between said source node and said constant voltage source; a first resistive element connected between said source node and said constant voltage source; and a series of a second resistive element and a diode element connected between said source node and said constant voltage source so as to supply a gate bias voltage from a node between said second resistive element and said diode element to said third node of said input matching circuit.