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US5845313A
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Direct logical block addressing flash memory mass storage architecture
Assignee: Micron Technology Inc
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Filing: 1995-07-31
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Granted: 1998-12-01
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Expires: 2015-07-31
Abstract
Abstract A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid erase cycles each time information stored in the mass storage is changed. Erase cycle are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address
Inventors
- 👤 Petro Estakhri
- 👤 Mahmud Assar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:45
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C29/765; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/023; G06F12/0238; G06F12/0246; G06F3/00; G06F3/06; G06F3/0601; G06F3/0602; G06F3/061; G06F3/0613; G06F3/0614; G06F3/0616; G06F3/0628; G06F3/0638; G06F3/064; G06F3/0668; G06F3/0671; G06F3/0673; G06F3/0679; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/10; G11C16/102; G11C29/78; G11C29/80; G11C29/816; G11C29/82; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1068
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
330 words
A mass storage device having nonvolatile memory, the storage device being coupled to an external digital system for storing binary information therefor in the nonvolatile memory, the external digital system including means for generating a plurality of logical block addresses for use in storing or reading data, the storage device comprising: a. a volatile memory device having a plurality of volatile memory locations each of which is uniquely addressable by one of the logical block addresses, and wherein each of the volatile memory locations is configured to store a physical block address without requiring the storage of a corresponding logical block address; b. one or more nonvolatile memory devices each having a plurality of nonvolatile data blocks, wherein each block is selectively programmable and erasable and further wherein each data block is uniquely addressable by one of the physical block addresses, and further wherein the plurality of nonvolatile data blocks has a plurality of used/free flags, one stored with each data block in the one or more nonvolatile memory devices for indicating whether a data block contains data; and c. a controller for receiving a block of data from the external digital system to be stored in the one or more nonvolatile memory devices, for receiving a target logical block address from the external system, for identifying a free data block within the nonvolatile data blocks having no data stored therein, for storing the physical block address of the free data block in the volatile memory location that corresponds to the target logical block address, and for periodically erasing all data blocks of the nonvolatile memory devices having flags which are set, whereby an erase cycle is not needed each time the external system writes to the storage device; wherein the used/free flags stored in the one or more nonvolatile memory devices which correlate to the physical block addresses of the plurality of nonvolatile data blocks are copied to the volatile memory locations during a power-up and a system reset.
Claim 2
Dependent Claim
330 words
A mass storage device having nonvolatile memory, the storage device being coupled to an external digital system for storing binary information therefor in the nonvolatile memory, the external digital system including means for generating a plurality of logical block addresses for use in storing or reading data, the storage device comprising: a. a volatile memory device having a plurality of volatile memory locations each of which is uniquely addressable by one of the logical block addresses, and wherein each of the volatile memory locations is configured to store a physical block address without requiring the storage of a corresponding logical block address; b. one or more nonvolatile memory devices each having a plurality of nonvolatile data blocks, wherein each block is selectively programmable and erasable and further wherein each data block is uniquely addressable by one of the physical block addresses, and further wherein the plurality of nonvolatile data blocks has a plurality of used/free flags, one stored with each data block in the one or more nonvolatile memory devices for indicating whether a data block contains data; and c. a controller for receiving a block of data from the external digital system to be stored in the one or more nonvolatile memory devices, for receiving a target logical block address from the external system, for identifying a free data block within the nonvolatile data blocks having no data stored therein, for storing the physical block address of the free data block in the volatile memory location that corresponds to the target logical block address, and for periodically erasing all data blocks of the nonvolatile memory devices having flags which are set, whereby an erase cycle is not needed each time the external system writes to the storage device; wherein the used/free flags stored in the one or more nonvolatile memory devices which correlate to the physical block addresses of the plurality of nonvolatile data blocks are copied to the volatile memory locations during a power-up and a system reset.
Claim 3
Dependent Claim
81 words
The device according to claim 1 further comprising means for addressing one of the plurality of volatile memory locations using a desired logical block address, means for retrieving a physical block address stored in the volatile memory location that corresponds to the desired logical block address, means for reading a data block within the nonvolatile memory devices identified by the retrieved physical block address and means for coupling the data block read from the nonvolatile memory device to the external system.
Claim 4
Dependent Claim
39 words
The device according to claim 2 further comprising a plurality of old/new flags, one stored with each data block in the one or more nonvolatile memory devices, for indicating whether the data block contains data that has been superseded.
Claim 5
Dependent Claim
46 words
The device of claim 3, wherein the old/new flags stored in the one or more nonvolatile memory devices which correlate to the physical block addresses of the plurality of nonvolatile data blocks are copied to the volatile memory locations during a power-up and a system reset.
Claim 6
Dependent Claim
28 words
The device according to claim 4 wherein each logical block address is also stored with one of the data blocks in the one or more nonvolatile memory devices.
Claim 7
Dependent Claim
56 words
The device according to claim 5 wherein the logical block addresses in the one or more nonvolatile memory devices which correlate to the physical block addresses of the plurality of nonvolatile data blocks are utilized in copying the used/free flags and the old/new flags to the volatile memory locations during a power-up and a system reset.
Claim 8
Dependent Claim
18 words
The device according to claim 1 wherein the flags which are set include old/new flags which are set.
Claim 9
Dependent Claim
13 words
The device according to claim 1 wherein the volatile memory comprise RAM cells.
References Cited (Backward Citations)
JPS62283496A
Cited
JPS62283497A
Cited
US5303198A
Cited
US5337275A
Cited
US5341330A
Cited
US5341339A
Cited
US5581723A
Cited
US5479638A
Cited
US5485595A
Cited
US5353256A
Cited
US5566314A
Cited
US5603001A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-30 | 2002-06-01 | 2002-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-30 | 2006-06-01 | 2006-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-30 | 2010-06-01 | 2010-12-01 | $7700.00 | Window Closed / Lapsed |