US5844844A
Expired / Lapsed
US
⏱️ 0.0 years remaining
FPGA memory element programmably triggered on both clock edges
Assignee: Xilinx Inc
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Filing: 1997-07-09
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Granted: 1998-12-01
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Expires: 2017-07-09
Abstract
Abstract A programmable memory element clocks in new data on both rising and falling edges of the clock, thereby optionally operating at twice the frequency of the distributed clock. The circuit according to the invention comprises two latches, one rising edge triggered and one falling edge triggered. One of these latches, each time the clock changes state, latches in a new value. When configured as a dual-edge flip-flop, the output of the inactive latch is fed forward to drive the output of the memory element. In one embodiment, the outputs of the two latches are multiplexed together and the clock selects the active output. According to a first embodiment of the invention, the memory element is used in an FPGA and can be programmed to function as either a latch or a dual-edge flip-flop. A second embodiment of the invention comprises a third latch. Based on the contents of a configuration memory cell, two of the three latches are selected to form a flip-flop. One such flip-flop is dual-edge, the other is single-edge. Further embodiments incorporate programmable variations of latches and flip-flops responsive to either or both clock edges.
Inventors
- 👤 Trevor J. Bauer
- 👤 Stephen M. Trimberger
- 👤 Steven P. Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:56
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
61 words
A programmable memory element having an output capable of changing on both rising and falling clock edges, comprising: a transparent low latch; a transparent high latch; programmable means for causing said transparent low latch to drive the memory element output during a first clock level and said transparent high latch to drive the memory element output during a second clock level.
Claim 2
Dependent Claim
61 words
A programmable memory element having an output capable of changing on both rising and falling clock edges, comprising: a transparent low latch; a transparent high latch; programmable means for causing said transparent low latch to drive the memory element output during a first clock level and said transparent high latch to drive the memory element output during a second clock level.
Claim 3
Dependent Claim
48 words
The programmable memory element of claim 1, wherein said programmable means for causing said transparent low latch to drive the memory element output during a first clock level and said transparent high latch to drive the memory element output during a second clock level comprises a programmable multiplexer.
Claim 4
Dependent Claim
19 words
The programmable memory element of claim 1, further comprising: means for programmably configuring the memory element as a latch.
Claim 5
Dependent Claim
24 words
The programmable memory element of claim 3, wherein said means for programmably configuring the memory element as a latch comprises a configuration memory cell.
Claim 6
Dependent Claim
34 words
The programmable memory element of claim 1, further comprising: means for programmably configuring the memory element as a transparent low latch; and means for programmably configuring the memory element as a transparent high latch.
Claim 7
Dependent Claim
22 words
The programmable memory element of claim 1, further comprising: means for programmably configuring the memory element as a rising edge triggered flip-flop.
Claim 8
Dependent Claim
22 words
The programmable memory element of claim 1, further comprising: means for programmably configuring the memory element as a falling edge triggered flip-flop.
Claim 9
Dependent Claim
36 words
The programmable memory element of claim 1, further comprising: means for programmably configuring the memory element as a rising edge triggered flip-flop; and means for programmably configuring the memory element as a falling edge triggered flip-flop.
Claim 10
Dependent Claim
89 words
A programmable memory element, comprising: an input line; an output line; a clock line; a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output; a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output; programmable means for selecting between said outputs of said first and second latches and placing said selected latch output on said output line.
Claim 11
Dependent Claim
89 words
A programmable memory element, comprising: an input line; an output line; a clock line; a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output; a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output; programmable means for selecting between said outputs of said first and second latches and placing said selected latch output on said output line.
Claim 12
Dependent Claim
41 words
The programmable memory element of claim 9, wherein said programmable means for selecting between said outputs of said first and second latches and placing said selected latch output on said output line comprises a programmable multiplexer controlled by said clock line.
Claim 13
Dependent Claim
19 words
The programmable memory element of claim 9, further comprising: means for programmably configuring the memory element as a latch.
Claim 14
Dependent Claim
24 words
The programmable memory element of claim 11, wherein said means for programmably configuring the memory element as a latch comprises a configuration memory cell.
Claim 15
Dependent Claim
34 words
The programmable memory element of claim 9, further comprising: means for programmably configuring the memory element as a transparent low latch; and means for programmably configuring the memory element as a transparent high latch.
Claim 16
Dependent Claim
22 words
The programmable memory element of claim 9, further comprising: means for programmably configuring the memory element as a rising edge triggered flip-flop.
Claim 17
Dependent Claim
22 words
The programmable memory element of claim 9, further comprising: means for programmably configuring the memory element as a falling edge triggered flip-flop.
Claim 18
Dependent Claim
36 words
The programmable memory element of claim 9, further comprising: means for programmably configuring the memory element as a rising edge triggered flip-flop; and means for programmably configuring the memory element as a falling edge triggered flip-flop.
Claim 19
Dependent Claim
91 words
A programmable memory element, comprising: an input line; an output line; a clock line; a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output; a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output; programmable means for selecting between said outputs of said first and second latches; and means for placing said selected latch output on said output line.
Claim 20
Dependent Claim
91 words
A programmable memory element, comprising: an input line; an output line; a clock line; a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output; a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output; programmable means for selecting between said outputs of said first and second latches; and means for placing said selected latch output on said output line.
Claim 21
Dependent Claim
31 words
The programmable memory element of claim 17, wherein said programmable means for selecting between said outputs of said first and second latches comprises a programmable multiplexer controlled by said clock line.
Claim 22
Dependent Claim
23 words
The programmable memory element of claim 17, wherein said means for placing said selected latch output on said output line comprises an inverter.
Claim 23
Dependent Claim
23 words
The programmable memory element of claim 17, wherein said means for placing said selected latch output on said output line comprises a buffer.
Claim 24
Dependent Claim
19 words
The programmable memory element of claim 17, further comprising: means for programmably configuring the memory element as a latch.
Claim 25
Dependent Claim
24 words
The programmable memory element of claim 21, wherein said means for programmably configuring the memory element as a latch comprises a configuration memory cell.
Claim 26
Dependent Claim
34 words
The programmable memory element of claim 17, further comprising: means for programmably configuring the memory element as a transparent low latch; and means for programmably configuring the memory element as a transparent high latch.
Claim 27
Dependent Claim
95 words
A programmable memory element, comprising: an input line; an output line; a clock line; a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output; a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output; a programmable multiplexer controlled by said clock line for selecting between said outputs of said first and second latches and placing said selected latch output on said output line.
Claim 28
Dependent Claim
95 words
A programmable memory element, comprising: an input line; an output line; a clock line; a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output; a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output; a programmable multiplexer controlled by said clock line for selecting between said outputs of said first and second latches and placing said selected latch output on said output line.
Claim 29
Dependent Claim
34 words
The programmable memory element of claim 24, further comprising: means for programmably configuring said memory element as a transparent low latch; and means for programmably configuring said memory element as a transparent high latch.
Claim 30
Dependent Claim
38 words
The programmable memory element of claim 24, further comprising: a configurable memory cell for configuring said memory element as a transparent low latch; and a configurable memory cell for configuring said memory element as a transparent high latch.
Claim 31
Dependent Claim
124 words
A programmable memory element, comprising: an input line; an output line; a clock line; a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output; a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output; a programmable multiplexer controlled by said clock line for selecting between said outputs of said first and second latches, said multiplexer having an output; a third latch for programmably latching said output of said multiplexer, said third latch having an output which drives said output line; and means for programmably configuring the memory element as a single-edge flip-flop.
Claim 32
Dependent Claim
124 words
A programmable memory element, comprising: an input line; an output line; a clock line; a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output; a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output; a programmable multiplexer controlled by said clock line for selecting between said outputs of said first and second latches, said multiplexer having an output; a third latch for programmably latching said output of said multiplexer, said third latch having an output which drives said output line; and means for programmably configuring the memory element as a single-edge flip-flop.
Claim 33
Dependent Claim
34 words
The programmable memory element of claim 27, further comprising: means for programmably configuring the memory element as a rising edge flip-flop; and means for programmably configuring the memory element as a falling edge flip-flop.
Claim 34
Dependent Claim
19 words
The programmable memory element of claim 27, further comprising: means for programmably configuring the memory element as a latch.
Claim 35
Dependent Claim
34 words
The programmable memory element of claim 27, further comprising: means for programmably configuring the memory element as a transparent high latch; and means for programmably configuring the memory element as a transparent low latch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-30 | 2002-06-01 | 2002-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-30 | 2006-06-01 | 2006-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-30 | 2010-06-01 | 2010-12-01 | $7700.00 | Window Closed / Lapsed |