Damage free gate dielectric process during gate electrode plasma etching

Abstract

Abstract In a CMOS device uses a thin oxide film as a gate dielectric film, gate electrode plasma etching frequently induces gate dielectric damage. This invention discloses a process which can form a damage free gate dielectric even though there is plasma nonuniformity during gate electrode etching. In this invention, a thin polysilicon layer is formed on the gate dielectric (gate oxide) layer and a thin oxide layer (not gate oxide) is formed on the thin polysilicon layer. The thin oxide layer (not gate oxide) is then patterned and etched to expose portions of the thin polysilicon layer. A thick polysilicon layer used to form the gate electrode is subsequently deposited. The thick polysilicon layer contacts the exposed portion of the underlying thin polysilicon layer, but is otherwise separated from the thin polysilicon layer by the thin oxide. The thin polysilicon layer is patterned and etched using a plasma etching process. The thin oxide (not the gate oxide) acts as an etching stop. There is no isolated polysilicon during the plasma etching process because there is a layer of thin polysilicon under the etching stop thin oxide layer. The thin polysilicon layer covers the substrate. The gate electrodes formed in the thick polysilicon layer contact the thin polysilicon layer so that surface currents in the thin polysilicon layer balance the local nonuniformity in conduction currents in the plasma. No charge builds up on the gate electrode regions and no gate oxide damage occurs.

Inventors

• 👤 Ming-Hsi Liu

Bibliographic Details