Protected zero-crossing detection using switching transistor's on-resistance

Claim 2

A circuit, comprising: first and second power transistors connected to turn on and turn off together; a first voltage-sensing stage which is operatively connected, through current-carrying terminals of said second transistor, to sense the voltage across current-carrying terminals of said first transistor; said first voltage-sensing stage being implemented without a type of transistor of said first transistor; wherein said first transistor is connected to interrupt a load current; whereby said second transistor protects said first voltage-sensing stage from voltages which may appear on said first transistor when said first transistor is off.

Claim 3

The circuit of claim 1, wherein said first power transistor is a field-effect transistor.

Claim 4

The circuit of claim 1, further comprising a motor controller connected to selectively turn on said first power transistor.

Claim 5

The circuit of claim 1, further comprising a heating means connected to be controlled by said first power transistor, and a control means connected to selectively turn on said first power transistor.

Claim 6

The circuit of claim 1, further comprising a transmitting device operatively connected to said first power transistor.

Claim 7

The circuit of claim 1, further comprising a power transformer connected to power a computer system.

Claim 8

The circuit of claim 1, wherein said first power transistor and said second power transistor are operatively connected to said first voltage-sensing stage on a secondary side of a transformer.

Claim 9

The circuit of claim 1, wherein said first power transistor and said second power transistor are vertical DMOS devices.

Claim 10

The circuit of claim 1, wherein said first voltage-sensing stage is on a secondary side of said transformer and operates as a master in a master-slave relationship with a second voltage-sensing stage on a primary side of said transformer.

Claim 11

The circuit of claim 1, wherein said first voltage-sensing stage is on a secondary side of a transformer and communicates with a second voltage-sensing stage on a primary side of said transformer, through a pulse transformer which is separate from said transformer.

Claim 12

The circuit of claim 1, wherein a second voltage-sensing stage on a primary side of a transformer turns a switch on or off in response to commands sent from said first voltage-sensing stage.

Claim 13

A circuit, comprising: first and second power transistors having respective control terminals thereof operatively connected in common; a first voltage-sensing stage having at least one input thereof operatively connected through current-carrying terminals of said second transistor to one of at least two current-carrying terminals of said first transistor, said first voltage-sensing stage being connected to detect zero-crossings in the voltage across said current-carrying terminals of said first transistor when said transistors are both on; said transistors both being implemented without a type of transistor of said first voltage-sensing stage; wherein said first transistor is connected to interrupt a load current; whereby said second transistor protects said first voltage-sensing stage from voltages which may appear on said first transistor when said first transistor is off.

Claim 14

A circuit, comprising: first and second power transistors having respective control terminals thereof operatively connected in common; a first voltage-sensing stage having at least one input thereof operatively connected through current-carrying terminals of said second transistor to one of at least two current-carrying terminals of said first transistor, said first voltage-sensing stage being connected to detect zero-crossings in the voltage across said current-carrying terminals of said first transistor when said transistors are both on; said transistors both being implemented without a type of transistor of said first voltage-sensing stage; wherein said first transistor is connected to interrupt a load current; whereby said second transistor protects said first voltage-sensing stage from voltages which may appear on said first transistor when said first transistor is off.

Claim 15

The circuit of claim 12, wherein said first power transistor is a field-effect transistor.

Claim 16

The circuit of claim 12, further comprising a motor controller connected to selectively turn on said first power transistor.

Claim 17

The circuit of claim 12 further comprising a heating means connected to be controlled by said first power transistor, and a control means connected to selectively turn on said first power transistor.

Claim 18

The circuit of claim 12, further comprising a transmitting device operatively connected to said first power transistor.

Claim 19

The circuit of claim 12, further comprising a power transformer connected to power a computer system.

Claim 20

The circuit of claim 12, wherein said first power transistor and said second power transistor are operatively connected to said first voltage-sensing stage which is on a secondary side of a transformer.

Claim 21

The circuit of claim 12, wherein said first power transistor and said second power transistor are vertical DMOS devices.

Claim 22

The circuit of claim 12, wherein said first voltage-sensing stage is on a secondary side of a transformer and operates as a master in a master-slave relationship with a second voltage-sensing stage on a primary side of said transformer.

Claim 23

The circuit of claim 12, wherein said first voltage-sensing stage on a secondary side of a transformer communicates with a second voltage-sensing stage on a primary side of said transformer through a pulse transformer which is separate from said transformer.

Claim 24

The circuit of claim 12, wherein a second voltage-sensing stage is on a primary side of a transformer and turns a switch on or off in response to commands sent from said second voltage-sensing stage.

Claim 25

A computer system, comprising: memory, and a microprocessor operatively connected to read and write said memory; a graphics controller connected to said microprocessor; a video display connected to said graphics controller; and a power supply, comprising first and second power transistors connected to turn on and turn off together; a voltage-sensing stage which is operatively connected, through current-carrying terminals of said second transistor, to sense the voltage across current-carrying terminals of said first transistor; said voltage-sensing stage being at least partly implemented using a device type different from that of said first transistor; wherein said first transistor is connected to interrupt a load current; whereby said second transistor protects said voltage-sensing stage from voltages which may appear on said first transistor when said first transistor is off.

Claim 26

A computer system, comprising: memory, and a microprocessor operatively connected to read and write said memory; a graphics controller connected to said microprocessor; a video display connected to said graphics controller; and a power supply, comprising first and second power transistors connected to turn on and turn off together; a voltage-sensing stage which is operatively connected, through current-carrying terminals of said second transistor, to sense the voltage across current-carrying terminals of said first transistor; said voltage-sensing stage being at least partly implemented using a device type different from that of said first transistor; wherein said first transistor is connected to interrupt a load current; whereby said second transistor protects said voltage-sensing stage from voltages which may appear on said first transistor when said first transistor is off.

Claim 27

The system of claim 23, wherein said first power transistor and said second power transistor are operatively connected to said first voltage-sensing stage which is on a secondary side of a transformer.

Claim 28

The system of claim 23, wherein said first power transistor and said second power transistor are vertical DMOS devices.

Claim 29

The system of claim 23, wherein said first voltage-sensing stage is on a secondary side of a transformer and operates as a master in a master-slave relationship with a second voltage-sensing stage on a primary side of said transformer.

Claim 30

The system of claim 23, wherein said first voltage-sensing stage is on a secondary side of a transformer and communicates with a second voltage-sensing stage on a primary side of said transformer through a pulse transformer which is separate from said transformer.

Claim 31

The system of claim 23, wherein a second voltage-sensing stage is on a primary side of a first transformer and turns a switch on or off in response to commands sent from said first voltage-sensing stage.

Claim 34

The method of claim 29, wherein said first power transistor and said second power transistor are operatively connected to said first voltage-monitoring circuit on a secondary side of a transformer.

Claim 35

The method of claim 29, wherein said first voltage-monitoring circuit on a secondary side of a transformer operates as a master in a master-slave relationship with a second voltage-monitoring circuit on a primary side of said transformer.

Claim 36

The method of claim 29, wherein said first voltage-monitoring circuit operatively connected on a secondary side of a transformer communicates with a second voltage-monitoring circuit on a primary side of said transformer, through a pulse transformer.

Claim 37

The method of claim 29, wherein said first power transistor and said second power transistor are vertical DMOS devices.

Claim 38

A circuit for zero-crossing detection of currents in power circuits, comprising: means for isolating a first power transistor from a first voltage-monitoring circuit with a second power transistor, which is switched on only when said first power transistor is switched on; said first power transistor also being connected to switch a load current; and means for detecting zero-crossings of said load current by detecting zero-crossings of a voltage on an on-resistance of said first power transistor, using said first voltage-monitoring circuit, when said second power transistor is on.

Claim 39

A circuit for zero-crossing detection of currents in power circuits, comprising: means for isolating a first power transistor from a first voltage-monitoring circuit with a second power transistor, which is switched on only when said first power transistor is switched on; said first power transistor also being connected to switch a load current; and means for detecting zero-crossings of said load current by detecting zero-crossings of a voltage on an on-resistance of said first power transistor, using said first voltage-monitoring circuit, when said second power transistor is on.

Claim 40

The circuit of claim 34, wherein said first power transistor and said second power transistor are operatively connected to said first voltage-monitoring circuit on a secondary side of a transformer.

Claim 41

The circuit of claim 34, wherein said first voltage-monitoring circuit on said secondary side of a transformer operates as a master in a master-slave relationship with a second voltage-monitoring circuit on a primary side of said transformer.

Claim 42

The circuit of claim 34, wherein said first voltage-monitoring circuit operatively connected on a secondary side of a transformer communicates with a second voltage-monitoring circuit on a primary side of said transformer, through a pulse transformer.

Claim 43

The circuit of claim 34, wherein said first power transistor and said second power transistor are vertical DMOS devices.