Abstract An EEPROM with separated floating gate to reduce the antenna ratio is disclosed. The structure of the EEPROM includes field oxides formed on a wafer. A control gate is formed in the wafer. A first gate oxide formed above the wafer for isolation. A first polysilicon portion is formed on the first gate oxide, which includes a gate for a transistor, a first contact window and a floating gate. Further, the floating gate is set above the control gate. A second gate oxide is formed on the wafer adjacent to the field oxide for isolation. A tunneling window is formed in the second gate oxide. A second polysilicon portion having a second contact window is formed on the second gate oxide. A dielectric layer is formed on the first polysilicon portion and the second polysilicon portion. Contact holes are formed in the dielectric layer and a connecting structure formed in the contact holes and on the dielectric layer for interconnection.
A method of forming a EEPROM having a separated floating gate on a wafer, said method comprising: forming a control gate in said wafer by ion implantation; forming a gate oxide layer on said wafer; forming a tunneling window in a portion of said gate oxide; forming a polysilicon layer on said gate oxide and said tunneling window; separating said polysilicon layer into a first portion and a second portion using a first mask, wherein said first portion is used to define a gate of a transistor, a first contact window and a floating gate, and wherein said second portion is used to define a second contact window; removing said first mask; forming a dielectric layer on said polysilicon layer; patterning and etching said dielectric layer using a second mask to define a first contact hole and a second contact hole, wherein said first contact hole is connected to said first contact window and wherein said second contact hole is connected to said second contact window; removing said second mask; and forming a metal layer in said first contact hole, second contact hole and on said dielectric layer.
Claim 2
Independent Claim
188 words
A method of forming a EEPROM having a separated floating gate on a wafer, said method comprising: forming a control gate in said wafer by ion implantation; forming a gate oxide layer on said wafer; forming a tunneling window in a portion of said gate oxide; forming a polysilicon layer on said gate oxide and said tunneling window; separating said polysilicon layer into a first portion and a second portion using a first mask, wherein said first portion is used to define a gate of a transistor, a first contact window and a floating gate, and wherein said second portion is used to define a second contact window; removing said first mask; forming a dielectric layer on said polysilicon layer; patterning and etching said dielectric layer using a second mask to define a first contact hole and a second contact hole, wherein said first contact hole is connected to said first contact window and wherein said second contact hole is connected to said second contact window; removing said second mask; and forming a metal layer in said first contact hole, second contact hole and on said dielectric layer.
Claim 3
Dependent Claim
32 words
The method of claim 1 further including the steps of: patterning a third mask on said metal layer; etching said metal layer by using said third mask; and stripping said third mask.