US5837557A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor fabrication method of forming a master layer to combine individually printed blocks of a circuit pattern
Assignee: Advanced Micro Devices Inc
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Filing: 1997-03-14
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Granted: 1998-11-17
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Expires: 2017-03-14
Abstract
Abstract Each circuit block of a plurality of circuit blocks on a semiconductor substrate is imaged in an exposure field defined by a reticle. The circuit blocks are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The circuit blocks are globally interconnected by depositing a blanket metal layer, masking the metal layer and etching the metal layer using a stitching reticle having an exposure field overlapping the plurality of circuit blocks. The combination of reticle-imaged circuit blocks allows each individual circuit block to be fabricated independently, using independent imaging resolution, layout rules, design rules, different polysilicon sizes and source/drain region sizes and the like. In addition different reticles, including different reticle types, resolutions and qualities may be used to construct the various circuit blocks. Different imaging technologies may be used to construct the independent circuit blocks, including X-ray, I-line, H-line, ion-beam and electron-beam irradiation, for example. While the different circuit blocks are independently constructed, the circuit blocks are globally interconnected using the blanket metal layer so that overall circuit size is reduced, circuit quality is enhanced, fabrication time and costs are reduced, and performance is increased. A plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are globally interconnected using a blanket metal layer that is imaged using a stitch mask and etch operation that combines and electrically connects the individual integrated chips.
Inventors
- 👤 H. Jim Fulford, Jr.
- 👤 Robert Dawson
- 👤 Mark I. Gardner
- 👤 Frederick N. Hause
- 👤 Mark W. Michael
- 👤 Bradley T. Moore
- 👤 Derick J. Wristers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:47
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0186; H10D84/02; H10D84/03; H10D84/038; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
145 words
A method of fabricating an integrated circuit comprising the steps of: fabricating a plurality of electronically and spatially independent device regions extending laterally on a substrate wafer, the semiconductor device regions being electrically isolated by an isolation; individually patterning the regions of the plurality of device regions; etching the plurality of device regions in accordance with the individual patterning of the regions; depositing an insulating layer overlying the plurality of device regions on the substrate wafer; forming a plurality of patterned vias extending through the insulating layer to selected locations of the plurality of device regions; depositing a conductive material in the vias electrically-coupled to the selected locations of the plurality of device regions; and depositing a conductive master layer overlying the insulating layer and extending laterally overlying the plurality of device regions, the conductive master layer electrically-coupling to the conductive material in the vias.
Claim 2
Independent Claim
145 words
A method of fabricating an integrated circuit comprising the steps of: fabricating a plurality of electronically and spatially independent device regions extending laterally on a substrate wafer, the semiconductor device regions being electrically isolated by an isolation; individually patterning the regions of the plurality of device regions; etching the plurality of device regions in accordance with the individual patterning of the regions; depositing an insulating layer overlying the plurality of device regions on the substrate wafer; forming a plurality of patterned vias extending through the insulating layer to selected locations of the plurality of device regions; depositing a conductive material in the vias electrically-coupled to the selected locations of the plurality of device regions; and depositing a conductive master layer overlying the insulating layer and extending laterally overlying the plurality of device regions, the conductive master layer electrically-coupling to the conductive material in the vias.
Claim 3
Dependent Claim
38 words
A method according to claim 1, further comprising the steps of: patterning the conductive master layer using a pattern extending laterally over the spatially independent device regions; and etching the conductive master layer in accordance with the patterning.
Claim 4
Dependent Claim
27 words
A method according to claim 2, further comprising the steps of: stitching the conductive master layer to form connections among the plurality of spatially independent device regions.
Claim 5
Dependent Claim
15 words
A method according to claim 1, wherein the conductive master layer forms a power bus.
Claim 6
Dependent Claim
16 words
A method according to claim 1, wherein the conductive master layer forms a global signal line.
Claim 7
Dependent Claim
35 words
A method according to claim 1, wherein the plurality of mutually disconnected and nonoverlapping semiconductor device regions are individually masked using a reticle and lens confining a mask image to the corresponding semiconductor device region.
Claim 8
Dependent Claim
65 words
A method according to claim 1 further comprising the steps of: patterning the conductive master layer using a pattern extending laterally over the spatially independent device regions; and etching the conductive master layer in accordance with the patterning; wherein the conductive master layer is patterned using a reticle and lens generating a mask image overlapping a plurality of the disconnected and nonoverlapping semiconductor device regions.
Claim 9
Dependent Claim
105 words
A method according to claim 1 further comprising the steps of: patterning the conductive master layer using a pattern extending laterally over the spatially independent device regions; and etching the conductive master layer in accordance with the patterning; wherein: the plurality of electronically and spatially independent device regions are individually masked using a reticle and lens confining a mask image to the corresponding semiconductor device region; the conductive master layer is patterned using a reticle and lens generating a mask image overlapping a plurality of the disconnected and nonoverlapping semiconductor device regions; and the device region reticles and the overlapping reticle have the same resolution.
Claim 10
Dependent Claim
108 words
A method according to claim 1 further comprising the steps of: patterning the conductive master layer using a pattern extending laterally over the spatially independent device regions; and etching the conductive master layer in accordance with the patterning; wherein: the plurality of electronically and spatially independent device regions are individually masked using a reticle and lens confining a mask image to the corresponding semiconductor device region; the conductive master layer is patterned using a reticle and lens generating a mask image overlapping a plurality of the disconnected and nonoverlapping semiconductor device regions; and the resolution of the device region reticles is higher than resolution of the overlapping reticle.
Claim 11
Dependent Claim
37 words
A method according to claim 1 wherein the step of fabricating a plurality of electronically and spatially independent device regions includes the step of fabricating a plurality of different integrated circuits including a microprocessor and a memory.
Claim 12
Independent Claim
77 words
A method of fabricating an integrated circuit comprising the steps of: independently fabricating a plurality of laterally and electrically separate integrated circuit regions on a substrate wafer using independent imaging of the separate integrated circuit regions; depositing a conductive master layer on the substrate overlying the plurality of laterally and electrically separate integrated circuit regions; and patterning the conductive master layer using a single imaging extending over a plurality of laterally and electrically separate integrated circuit regions.
Claim 13
Independent Claim
77 words
A method of fabricating an integrated circuit comprising the steps of: independently fabricating a plurality of laterally and electrically separate integrated circuit regions on a substrate wafer using independent imaging of the separate integrated circuit regions; depositing a conductive master layer on the substrate overlying the plurality of laterally and electrically separate integrated circuit regions; and patterning the conductive master layer using a single imaging extending over a plurality of laterally and electrically separate integrated circuit regions.
Claim 14
Dependent Claim
38 words
A method according to claim 11, further comprising the steps of: etching the conductive master layer in accordance with the patterning; and stitching the conductive master layer to form connections among the plurality of spatially independent device regions.
Claim 15
Dependent Claim
15 words
A method according to claim 11, wherein the conductive master layer is a metal layer.
Claim 16
Dependent Claim
15 words
A method according to claim 11, wherein the conductive master layer is a polysilicon layer.
Claim 17
Dependent Claim
15 words
A method according to claim 11, wherein the conductive master layer forms a power bus.
Claim 18
Dependent Claim
16 words
A method according to claim 11, wherein the conductive master layer forms a global signal line.
Claim 19
Dependent Claim
35 words
A method according to claim 11, wherein the plurality of laterally and electrically separate integrated circuit regions are individually masked using a reticle and lens confining a mask image to the corresponding integrated circuit region.
Claim 20
Dependent Claim
66 words
A method according to claim 11 further comprising the steps of: patterning the conductive master layer using a pattern extending laterally over the separate integrated circuit regions; and etching the conductive master layer in accordance with the patterning; wherein the conductive master layer is patterned using a reticle and lens generating a mask image overlapping a plurality of the disconnected and nonoverlapping separate integrated circuit regions.
Claim 21
Dependent Claim
109 words
A method according to claim 11 further comprising the steps of: patterning the conductive master layer using a pattern extending laterally over the laterally and electrically separate integrated circuit regions; and etching the conductive master layer in accordance with the patterning; wherein: the plurality of laterally and electrically separate integrated circuit regions are individually masked using a reticle and lens confining a mask image to the corresponding semiconductor device region; the conductive master layer is patterned using a reticle and lens generating a mask image overlapping a plurality of the disconnected and nonoverlapping semiconductor device regions; and the device region reticles and the overlapping reticle have the same resolution.
Claim 22
Dependent Claim
38 words
A method according to claim 11 wherein the step of fabricating a plurality of laterally and electrically separate integrated circuit regions includes the step of fabricating a plurality of different integrated circuits including a microprocessor and a memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-16 | 2010-05-18 | 2010-11-17 | $7700.00 | Window Closed / Lapsed |