US5835751A
Expired / Lapsed
US
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Structure and method for providing reconfigurable emulation circuit
Assignee: Cadence Design Systems Inc
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Filing: 1997-07-11
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Granted: 1998-11-10
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Expires: 2017-07-11
Abstract
Abstract A method and a structure provide emulation circuit implemented on a logic block module comprising clocked and unclocked field programmable logic devices (FPGAs). Software modules analyze the target logic circuit and impose delay constraints to require certain storage instances to be implemented on separate FPGAs so as to prevent hold time violation artifacts.
Inventors
- 👤 Nang-Ping Chen
- 👤 Robert J. Ko
- 👤 Jeong-Tyng Li
- 👤 Thomas B. Huang
- 👤 Ming-Yang Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 09:50
CPC Classifications
A; A21; A21B; A21B1/00; A21B1/02; A21B1/24; A21B1/245; G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331; G06F30/34
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
94 words
In implementing an emulation circuit from a netlist description of a design, said design receiving a plurality of clock sources, a structure comprising: means for importing said netlist description into a data structure representing said design; means for analyzing said data structure to identify, for each storage instance receiving a clock signal in said design, a clock path connecting said clock signal to one of said clock sources from which said clock signal is derived; and means for implementing a portion of each clock path in a programmable logic device dedicated for clock generation.
Claim 2
Dependent Claim
94 words
In implementing an emulation circuit from a netlist description of a design, said design receiving a plurality of clock sources, a structure comprising: means for importing said netlist description into a data structure representing said design; means for analyzing said data structure to identify, for each storage instance receiving a clock signal in said design, a clock path connecting said clock signal to one of said clock sources from which said clock signal is derived; and means for implementing a portion of each clock path in a programmable logic device dedicated for clock generation.
Claim 3
Dependent Claim
126 words
A structure as in claim 1, further comprising: means for identifying, for each of said storage instances, data paths starting from either (i) an output data terminal of another storage instance, or (ii) a input terminal of said design, and leading to an input terminal of said storage instance, said data paths including combinatorial circuits; means for clustering, for each of said storage instance, said storage instance and said data paths in a cluster; and means for implementing said emulation circuit in a plurality of programmable devices using a method which prefers implementing the data paths and the storage instance of a cluster in the same programmable logic device to implementing said data paths and said storage instance of a cluster in separate programmable logic devices.
Claim 4
Dependent Claim
65 words
A structure as in claim 2, further comprising means for constructing a connectivity graph for identifying common signals between a pair of clusters, and wherein said means for implementing said emulation circuit uses a method which prefers implementing a pair of clusters having common signals in the same programmable logic device to implementing a pair of clusters having said common signals in separate programmable devices.
Claim 5
Dependent Claim
47 words
A structure as in claim 2, further comprising means for identifying common components between each pair of clusters, and wherein said means for implementing said emulation circuit duplicates, when said clusters are implemented in different programmable devices, said common components in each of said different programmable devices.
References Cited (Backward Citations)
US5715172A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |