US5834848A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic device and semiconductor package
Assignee: Toshiba Corp
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Filing: 1997-12-02
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Granted: 1998-11-10
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Expires: 2017-12-02
Abstract
Abstract The electronic device has a structure that a semiconductor package (10) is mounted on a motherboard (21), and a buffer layer (41) for relieving a stress, which is produced due to a difference of physical properties between the semiconductor package (10) and the motherboard (21), is mounted on the electrical and mechanical interface between the semiconductor package (10) and the motherboard (21). For example, the buffer layer (41) having a thermal expansion coefficient close to that of the motherboard (21) is formed on a face of the semiconductor package 10 having an external connecting terminals (12b) mounted. A stress caused due to a difference between a thermal expansion coefficient of a wiring substrate (12) of the semiconductor package and that of the motherboard (21) can be relieved by the buffer layer (41). Therefore, a cyclic stress applied to the connection between the semiconductor package and the motherboard in the actual application environment can be relieved, and reliability of connection can be improved. Thus, a semiconductor package mountable with a high degree of reliability and an electronic device having a high degree of reliability is provided.
Inventors
- 👤 Ken Iwasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:24
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/303; H10; H10W; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H05K2201/00; H05K2201/06; H05K2201/068; H05K2201/09; H05K2201/09818; H05K2201/09909; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10734; H05K2201/20; H05K2201/2036; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H05K3/3436; H10W72/00; H10W72/851; H10W72/853; H10W72/856; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734; Y; Y02; Y02P; Y02P70/00; Y02P70/50
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
231 words
An electronic device, comprising: a first wiring substrate having a first face, the first face of the first wiring substrate having a first region and a second region, connecting terminals formed on the first region, and the first wiring substrate having a first thermal expansion coefficient; a semiconductor package comprises, a second wiring substrate having a first face and a second face, the first face of the second wiring substrate having a first region and a second region, the first connecting terminals in the first region which are faced with the connecting terminals of the first substrate, second connecting terminals formed on the second face which are connected with the first connecting terminals, and the second wiring substrate having a second thermal expansion coefficient, and at least one semiconductor chip mounted on the second face of the second wiring substrate, and the semiconductor chip having electrodes connected with the second connecting terminals; connecting means for connecting the connecting terminals of the first wiring substrate and the first connecting terminals of the second wiring substrate; and, a buffer layer interposed between the second region of the first face of the first wiring substrate and the second region of the first face of the second wiring substrate, the buffer layer having a third thermal expansion coefficient which is in the range between the first thermal expansion coefficient and the second thermal expansion coefficient.
Claim 2
Dependent Claim
231 words
An electronic device, comprising: a first wiring substrate having a first face, the first face of the first wiring substrate having a first region and a second region, connecting terminals formed on the first region, and the first wiring substrate having a first thermal expansion coefficient; a semiconductor package comprises, a second wiring substrate having a first face and a second face, the first face of the second wiring substrate having a first region and a second region, the first connecting terminals in the first region which are faced with the connecting terminals of the first substrate, second connecting terminals formed on the second face which are connected with the first connecting terminals, and the second wiring substrate having a second thermal expansion coefficient, and at least one semiconductor chip mounted on the second face of the second wiring substrate, and the semiconductor chip having electrodes connected with the second connecting terminals; connecting means for connecting the connecting terminals of the first wiring substrate and the first connecting terminals of the second wiring substrate; and, a buffer layer interposed between the second region of the first face of the first wiring substrate and the second region of the first face of the second wiring substrate, the buffer layer having a third thermal expansion coefficient which is in the range between the first thermal expansion coefficient and the second thermal expansion coefficient.
Claim 3
Dependent Claim
24 words
An electronic device as set forth in claim 1, wherein the first thermal expansion coefficient and the third thermal expansion coefficient are approximately same.
Claim 4
Dependent Claim
39 words
An electronic device as set forth in claim 1, wherein a gap between the first face of the first wiring substrate and the first face of the second wiring substrate are equal to a thickness of the buffer layer.
Claim 5
Dependent Claim
53 words
An electronic device as set forth in claim 1, wherein the first wiring substrate comprising at least one wiring layer and at least one insulating layer insulating layer made of resin, and the second wiring substrate comprising a plurality of wiring layers and at least one insulating layer insulating layer made of ceramics.
Claim 6
Dependent Claim
16 words
An electronic device as set forth in claim 1, wherein the connecting means are solder bumps.
Claim 7
Dependent Claim
46 words
An electronic device as set forth in claim 5, wherein the buffer layer having a shape so as to maintain a gap between the first face of the first wiring substrate and the first face of the second wiring substrate flat when solder bumps are melted.
Claim 8
Dependent Claim
23 words
An electronic device as set forth in claim 1, wherein the buffer layer is formed along diagonal lines of the second wiring substrate.
Claim 9
Dependent Claim
38 words
An electronic device as set forth in claim 1, wherein the buffer layer having a lamination of a first buffer layer connected with the first wiring substrate and a second buffer layer connected with the second wiring substrate.
Claim 10
Dependent Claim
31 words
An electronic device as set forth in claim 8, wherein a thermal expansion coefficient of the first buffer layer is larger than a thermal expansion coefficient of the second buffer layer.
Claim 11
Dependent Claim
28 words
An electronic device as set forth in claim 1, wherein the third thermal expansion coefficient is in the range from about 0.5×10 -5 to about 1.8×10 -5 .
Claim 12
Dependent Claim
141 words
A semiconductor package, comprising: a wiring substrate having a first face and a second face, the first face of the second wiring substrate having a first region and a second region, the first connecting terminals in the first region, second connecting terminals formed on the second face which are connected with the first connecting terminals, and the second wiring substrate having a second thermal expansion coefficient; at least one semiconductor chip mounted on the second face of the second wiring substrate, and the semiconductor chip having electrodes connected with the second connecting terminals; solder bumps formed on the first connecting terminal of the second substrate; and, a buffer layer formed on the second region of the first face of the second wiring substrate, the buffer layer having a thickness which is approximately the same with a height of the solder bumps.
Claim 13
Dependent Claim
141 words
A semiconductor package, comprising: a wiring substrate having a first face and a second face, the first face of the second wiring substrate having a first region and a second region, the first connecting terminals in the first region, second connecting terminals formed on the second face which are connected with the first connecting terminals, and the second wiring substrate having a second thermal expansion coefficient; at least one semiconductor chip mounted on the second face of the second wiring substrate, and the semiconductor chip having electrodes connected with the second connecting terminals; solder bumps formed on the first connecting terminal of the second substrate; and, a buffer layer formed on the second region of the first face of the second wiring substrate, the buffer layer having a thickness which is approximately the same with a height of the solder bumps.
Claim 14
Dependent Claim
23 words
A semiconductor package as set forth in claim 11, wherein the buffer layer is formed along diagonal lines of the second wiring substrate.
Claim 15
Dependent Claim
129 words
A semiconductor package, comprising: a wiring substrate having a first face and a second face, the first face of the second wiring substrate having a first region and a second region, the first connecting terminals in the first region, second connecting terminals formed on the second face which are connected with the first connecting terminals, and the second wiring substrate having a second thermal expansion coefficient; at least one semiconductor chip mounted on the second face of the second wiring substrate, and the semiconductor chip having electrodes connected with the second connecting terminals; and, a buffer layer formed on the second region of the first face of the second wiring substrate, the buffer layer having a third thermal expansion coefficient which is larger than the second thermal expansion coefficient.
Claim 16
Dependent Claim
129 words
A semiconductor package, comprising: a wiring substrate having a first face and a second face, the first face of the second wiring substrate having a first region and a second region, the first connecting terminals in the first region, second connecting terminals formed on the second face which are connected with the first connecting terminals, and the second wiring substrate having a second thermal expansion coefficient; at least one semiconductor chip mounted on the second face of the second wiring substrate, and the semiconductor chip having electrodes connected with the second connecting terminals; and, a buffer layer formed on the second region of the first face of the second wiring substrate, the buffer layer having a third thermal expansion coefficient which is larger than the second thermal expansion coefficient.
Claim 17
Dependent Claim
31 words
A semiconductor package as set forth in claim 13, wherein the second wiring substrate comprising a plurality of wiring layers and at least one insulating layer insulating layer made of ceramics.
Claim 18
Dependent Claim
28 words
A semiconductor package as set forth in claim 14, wherein the third thermal expansion coefficient is in the range from about 0.5×10 -5 to about 1.8×10 -5 .
Claim 19
Dependent Claim
24 words
A semiconductor package as set forth in claim 13 further comprising conductive bumps formed on the second connecting terminals of the second wiring substrate.
Claim 20
Dependent Claim
16 words
A semiconductor package as set forth in claim 16, wherein the conductive bumps are solder bumps.
Claim 21
Dependent Claim
25 words
An electronic device as set forth in claim 16, wherein the thickness of the buffer layer is larger than the height of the solder bumps.
Claim 22
Dependent Claim
23 words
An electronic device as set forth in claim 13, wherein the second region is formed along diagonal lines of the second wiring substrate.
Claim 23
Dependent Claim
54 words
An electronic device as set forth in claim 13, wherein the buffer layer having a lamination of a first buffer layer and a second buffer layer connected with the second wiring substrate, and the thermal expansion coefficient of the first buffer layer is larger than a thermal expansion coefficient of the second buffer layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |