US5831465A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Variable delay circuit
Assignee: Renesas Electronics Corp
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Filing: 1997-03-31
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Granted: 1998-11-03
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Expires: 2017-03-31
Abstract
Abstract A variable delay circuit for arbitrarily change of a signal delay helps easily attain a desired resolution with a high precision, which has been difficult due to device process dependence of a voltage control circuit applying a voltage to a CMOS circuit. A variable voltage controller is provided between a power source and a CMOS circuit propagating a signal such that a delay time of signal propagation is supervised by controlling the voltage at a connecting point in the variable voltage controller. The controller includes two MOS transistors and an npn transistor, which solves the process dependence and hence leads to a low power consumption and a high resolution.
Inventors
- 👤 Seiichi Watarai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:31
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
264 words
A variable delay circuit comprising: a first delay generating circuit including a first MOS transistor of a first conduction type and a second MOS transistor of a second conduction type, the first delay generating circuit having a first input terminal connected to a gate of the first MOS transistor and a gate of the second MOS transistor, a first output terminal connected to a drain of the first MOS transistor and a drain of the second MOS transistor, a source of the first MOS transistor connected to a first variable voltage terminal, a source of the second MOS transistor connected to a second variable voltage terminal, the first input terminal further connected to a signal input terminal, and the first output terminal further connected to a signal output terminal; and a first variable voltage control means inserted between the first variable voltage terminal and a first power source, including third and fourth MOS transistors of the first conduction type and a first bipolar transistor, the third MOS transistor having its gate connected to a reference voltage input terminal and its source connected to the first power source, the fourth MOS transistor having its gate connected to a second power source and its drain connected to the first variable voltage terminal, and the first bipolar transistor having its base connected to the drain of the third MOS transistor and a source of the fourth MOS transistor, its collector connected to the first power source, and its emitter connected to the first variable voltage terminal, the second variable voltage terminal connected to the second power source.
Claim 2
Dependent Claim
264 words
A variable delay circuit comprising: a first delay generating circuit including a first MOS transistor of a first conduction type and a second MOS transistor of a second conduction type, the first delay generating circuit having a first input terminal connected to a gate of the first MOS transistor and a gate of the second MOS transistor, a first output terminal connected to a drain of the first MOS transistor and a drain of the second MOS transistor, a source of the first MOS transistor connected to a first variable voltage terminal, a source of the second MOS transistor connected to a second variable voltage terminal, the first input terminal further connected to a signal input terminal, and the first output terminal further connected to a signal output terminal; and a first variable voltage control means inserted between the first variable voltage terminal and a first power source, including third and fourth MOS transistors of the first conduction type and a first bipolar transistor, the third MOS transistor having its gate connected to a reference voltage input terminal and its source connected to the first power source, the fourth MOS transistor having its gate connected to a second power source and its drain connected to the first variable voltage terminal, and the first bipolar transistor having its base connected to the drain of the third MOS transistor and a source of the fourth MOS transistor, its collector connected to the first power source, and its emitter connected to the first variable voltage terminal, the second variable voltage terminal connected to the second power source.
Claim 3
Dependent Claim
132 words
A variable delay circuit as in claim 1, further comprising a second variable voltage control means inserted between the second variable voltage terminal and the second power source, including fifth and sixth MOS transistors of the second conduction type and a second bipolar transistor, the fifth MOS transistor having its gate connected to the reference voltage input terminal, and its source connected to the second power source, the sixth MOS transistor having its gate connected to the first power source, and its drain connected to the second variable voltage terminal, the second bipolar transistor having its base connected to the drain of the fifth MOS transistor and the source of the sixth MOS transistor, its collector connected to the second variable voltage terminal, and its emitter connected to the second power source.
Claim 4
Dependent Claim
66 words
A variable delay circuit as in claim 1, further comprising a seventh MOS transistor of the first conduction type, the seventh MOS transistor having its drain connected to the signal output terminal together with an input terminal of a first inverter (a first inversion logic circuit), its gate connected to an output terminal of the first inverter, and its source connected to the first power source.
Claim 5
Dependent Claim
103 words
A variable delay circuit as in claim 3, further comprising an eighth MOS transistor of the second conduction type, the eighth MOS transistor having its drain connected to the signal output terminal together with the drain of the seventh MOS transistor of the first conduction type and the input terminal of the first inverter (the first inversion logic circuit), its gate connected to the output terminal of the first inverter together with the gate of the seventh MOS transistor, and its source connected to the second power source while the source of the seventh MOS transistor is connected to the first power source.
Claim 6
Dependent Claim
65 words
A variable delay circuit as in claim 4, further comprising a second delay generating circuit, the second delay generating circuit inserted between the first output terminal of the first delay generating circuit and the signal output terminal, its first input terminal being connected to the first output terminal of the first delay generating circuit, and its first output terminal connected to the signal output terminal.
Claim 7
Dependent Claim
76 words
A variable delay circuit as in claim 5, further comprising a ninth MOS transistor of the second conduction type, the ninth MOS transistor having its source and drain between the signal output terminal and the first output terminal of the second delay generating circuit, its source being connected to the signal output terminal, its drain connected to the output terminal of the second delay generating circuit, and its gate connected to the first variable voltage terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-02 | 2002-05-04 | 2002-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-02 | 2006-05-04 | 2006-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-02 | 2010-05-04 | 2010-11-03 | $7700.00 | Window Closed / Lapsed |