Compiling apparatus and method for promoting an optimization effect of a program

Claim 2

A compiling apparatus for scheduling instructions by rearranging the instructions after allotting registers to object data for each of the instructions in a program, comprising: register information collecting means for collecting availability register information of the registers after once allotting the availability register information in a scheduling range in which the instructions are rearranged; instruction dependency analyzing means for analyzing dependency relating to definition of and reference to the registers among the object data for the instructions in the program; register renaming means for replacing at least one of the registers after once being allotted to the object data in the instructions based on intermediate text with at least one of the other registers according to an output of said register information collecting means and an output of said instruction dependency analyzing means; and an instruction schedule process unit for scheduling said instructions based on the at least one of the other registers generated by said register renaming means.

Claim 3

The compiling apparatus according to claim 1, further comprising: register information storage means for storing the register information collected by said register information collecting means; wherein said register information storage means stores, for each of a plurality of scheduling ranges in the program, information about a register not required in the scheduling range, a register used in the scheduling range, a register entered as an alive register in the scheduling range, and a register exiting as the alive register from the scheduling range.

Claim 4

The compiling apparatus according to claim 1, further comprising: register information storage means for storing the register information generated by said register renaming means; and debug information output means for outputting the register information which is collected by said register information collecting means and stored in said register information storage means, in the form of characters as debug information.

Claim 5

The compiling apparatus according to claim 1, wherein: said register renaming means renames the registers for improving parallelism of processes by replacing the registers allotted to the object data with other registers; and said register renaming means renames the registers for reducing a number of the registers by using, in a single instruction; a source register which stores reference data also as a destination register which stores data obtained as a result of execution of the instruction.

Claim 6

The compiling apparatus according to claim 4, wherein said register renaming means sequentially retrieves the instructions in the scheduling range one by one in an execution order, determines whether the source register can also be used as the destination register in a retrieved instruction, and if the source register can also be used as the destination register in the retrieved instruction, assigns a same number as the destination register to the source register, and if the source register cannot also be used as the destination register in the retrieved function, sequentially determines whether a register renaming process which improves the parallelism of the processes is valid, and if the register renaming process is valid, replaces the register allotted to the object data with the other register.

Claim 7

The compiling apparatus according to claim 5, wherein said register renaming means determines whether the register renaming process is valid for a first retrieved instruction, and retrieves a next instruction in the execution order without renaming the registers for the first retrieved instruction if the register renaming process is invalid.

Claim 8

The compiling apparatus according to claim 5, wherein said register renaming means determines that the source register can also be used as the destination register based upon a first condition, a second condition, and a third condition existing, said first condition requiring that contents of the destination register defined in the instruction to be determined are referred to at least once in subsequent instructions within the scheduling range to which the instruction belongs, said second condition requiring that contents of the source register in the instruction to be determined are not referred to in the subsequent instructions, and said third condition requiring that contents of the destination register in the instruction to be determined are not referred to in any program after the scheduling range to which the instruction belongs.

Claim 9

The compiling apparatus according to claim 5, wherein said register renaming means stores a last reference position of the register in the instruction replaced in the register renaming process, and allows the register to be reused as an available register candidate if the instruction to be processed in the register renaming process after the instruction in which the register was replaced appears after the last reference position.

Claim 10

The compiling apparatus according to claim 4, wherein said register renaming means determines whether the source register is also usable as the destination register in each of entire instructions in one scheduling range, performs the register renaming process according to a determination result such that the source register is also usable as the destination register, and then performs the register renaming process in which the registers allotted to the object data are replaced with other registers for the entire instructions in the scheduling range.

Claim 11

The compiling apparatus according to claim 9, wherein said register renaming means determines that the source register can also be used as the destination register based upon a first condition, a second condition, and a third condition existing, said first condition requiring that contents of the destination register defined in the instruction to be determined are referred to at least once in subsequent instructions within the scheduling range to which the instruction belongs, said second condition requiring that contents of the source register in the instruction to be determined are not referred to in the subsequent instructions, said third condition requiring that contents of the destination register in the instruction to be determined are not referred to in any program after the scheduling range to which the instruction belongs.

Claim 12

The compiling apparatus according to claim 9, further comprising: architecture information storage means for storing architecture information of a computer in which the program to be compiled operates; wherein said register renaming means alters register renaming priority levels among a plurality of instructions for transferring one of the registers to one of the other registers based upon the intermediate text depending on the architecture information of the computer.

Claim 13

A compiling apparatus which schedules instructions after allotting registers to generate codes for an efficient parallel process of the instructions, said apparatus having a front-end unit for receiving and analyzing a source program, an optimization unit for optimizing an analysis result, a register allotting unit for allotting the registers to data to be processed as the analysis result, an instruction scheduling unit for rearranging the instructions, and a code output unit for outputting an object program, the instruction scheduling unit comprising: a register information collecting unit for collecting register information indicating a range of available registers; instruction dependency analyzing means for analyzing dependency of the instructions in definition and reference; register renaming means for renaming the registers by replacing register numbers used for the instructions with other register numbers according to the collected register information and the instruction dependency analysis result; and instruction schedule process means for rearranging the instructions according to the renaming of the registers.

Claim 14

A compiling apparatus which schedules instructions after allotting registers to generate codes for an efficient parallel process of the instructions, said apparatus having a front-end unit for receiving and analyzing a source program, an optimization unit for optimizing an analysis result, a register allotting unit for allotting the registers to data to be processed as the analysis result, an instruction scheduling unit for rearranging the instructions, and a code output unit for outputting an object program, the instruction scheduling unit comprising: a register information collecting unit for collecting register information indicating a range of available registers; instruction dependency analyzing means for analyzing dependency of the instructions in definition and reference; register renaming means for renaming the registers by replacing register numbers used for the instructions with other register numbers according to the collected register information and the instruction dependency analysis result; and instruction schedule process means for rearranging the instructions according to the renaming of the registers.

Claim 15

A compiling method for scheduling instructions by rearranging the instructions after allotting registers to object data for each of the instructions in a program, comprising the steps of: collecting availability information of the registers in a scheduling range in which the instructions are rearranged; analyzing dependency relating to definition of and reference to the registers among the instructions in the program; replacing at least one of the registers allotted to the object data in the instructions with at least one of the other registers according to an output of said register information collecting step and an output of said instruction dependency analyzing step; and scheduling said instructions based on a result generated by said register renaming step.

Claim 16

A compiling method for scheduling instructions by rearranging the instructions after allotting registers to object data for each of the instructions in a program, comprising the steps of: collecting availability information of the registers in a scheduling range in which the instructions are rearranged; analyzing dependency relating to definition of and reference to the registers among the instructions in the program; replacing at least one of the registers allotted to the object data in the instructions with at least one of the other registers according to an output of said register information collecting step and an output of said instruction dependency analyzing step; and scheduling said instructions based on a result generated by said register renaming step.