Large-capacity content addressable memory

Claim 1

A content addressable memory (CAM) chip comprising: an array of core cells of m rows×n columns, the core cells of each row being connected to the respective word line, the core cells of each column being connected to the respective bit line, the core cell including storage means for storing binary data; n comparator means, each being connected to the respective bit line; encoder means connected to the n comparator means via a match line; self-timing means for generating m clock pulse signals in response to an input clock signal fed to the chip, the m clock pulse signals being sequentially generated on-chip; means for selecting the row sequentially in response to the m clock pulse signals, so that the data stored in the n core cells of the selected row is readable by the n comparator means; and means for providing reference data of n bits, each bit data being fed to the respective one of the n comparator means, wherein the n comparator means compare the data read from the n core cells of the sequentially selected row to the n bit reference data and a comparison result row-by-row is provided via the match line to the encoder means, so that match operation results are provided from the encoder means.