US5827780A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Additive metalization using photosensitive polymer as RIE mask and part of composite insulator
Assignee: Promos Technologies Inc
•
Filing: 1996-04-01
•
Granted: 1998-10-27
•
Expires: 2016-04-01
Abstract
Abstract The surface of an integrated circuit, which uses reactive ion etching to pattern metal interconnection, is protected with two insulating layers on the surface. The first layer is a conventional silicon dioxide. The second layer is a photosensitive polymer which is the same as the material used for subsequent metalization of interconnection using the reactive ion etching technique. When the second layer is used, the reactive ion etching cannot attack the silicon dioxide. A trench can be cut through the two insulating layers, using a window in the photosensitive polymer as a mask, to serve as a via hole for metal to contact the substrate
Inventors
- 👤 Liang Choo Hsia
- 👤 Thomas Tong Long Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10P; H10P50/00; H10P50/73; H10W20/01; H10W20/071; H10W20/081; H10W20/084; H10W20/0888
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
80 words
An integrated circuit structure, comprising: a semiconductor substrate fabricated with various active and passive devices, an insulating layer covering said structure having a composite of a dielectric is lower layer and a photosensitive polymer as upper layer for protecting the integrity of said dielectric from any subsequent reactive ion etching and metal interconnection which is patterned by removing any excess metal deposited on top of said insulating layer with said reactive ion etching using said photosensitive polymer as a mask.
Claim 2
Dependent Claim
80 words
An integrated circuit structure, comprising: a semiconductor substrate fabricated with various active and passive devices, an insulating layer covering said structure having a composite of a dielectric is lower layer and a photosensitive polymer as upper layer for protecting the integrity of said dielectric from any subsequent reactive ion etching and metal interconnection which is patterned by removing any excess metal deposited on top of said insulating layer with said reactive ion etching using said photosensitive polymer as a mask.
Claim 3
Dependent Claim
23 words
An integrated circuit structure as described in claim 1, wherein said semiconductor substrate is a silicon substrate, and said dielectric is silicon dioxide.
Claim 4
Dependent Claim
22 words
An integrated circuit structure as described in claim 1, wherein said substrate is a silicon substrate and said dielectric is silicon nitride.
Claim 5
Dependent Claim
15 words
An integrated circuit structure as described in claim 1, wherein said photosensitive polymer is polyimide.
Claim 6
Dependent Claim
30 words
An integrated circuit structure as described in claim 1, wherein a trench is cut in said insulating layer as a via hole for a metal contact to said semiconductor substrate.
Claim 7
Dependent Claim
15 words
An integrated circuit as described in claim 5, wherein said trench is filled with metal.
Claim 8
Dependent Claim
22 words
An integrated circuit as described in claim 6, wherein said metal is selected from the group consisting of copper, aluminum and tungsten.
Claim 9
Dependent Claim
17 words
An integrated circuit as described in claim 1, wherein said metal interconnection is planarized by chemical-mechanical process.
Claim 10
Independent Claim
134 words
A method of fabricating an integrated circuit having a semiconductor substrate covered with a first insulating layer, comprising the steps of: coating over said first insulating layer a second insulating layer of photosensitive polymer, which is resistant to reactive ion etching when cured, patterning said photosensitive polymer using a mask, curing said photosensitive polymer, etching said first insulating layer using said photosensitive polymer as a mask to form a trench, without removing said photosensitive polymer, depositing a metal to form said trench to form a contact with said substrate, removing any excess metal deposited said trench and planarizing the surface of said photosensitive polymer, and metalizing said surface for interconnection and patterning said interconnection with said reactive ion etching without affecting the integrity of said first insulating layer with protection from said photosensitive polymer.
Claim 11
Independent Claim
134 words
A method of fabricating an integrated circuit having a semiconductor substrate covered with a first insulating layer, comprising the steps of: coating over said first insulating layer a second insulating layer of photosensitive polymer, which is resistant to reactive ion etching when cured, patterning said photosensitive polymer using a mask, curing said photosensitive polymer, etching said first insulating layer using said photosensitive polymer as a mask to form a trench, without removing said photosensitive polymer, depositing a metal to form said trench to form a contact with said substrate, removing any excess metal deposited said trench and planarizing the surface of said photosensitive polymer, and metalizing said surface for interconnection and patterning said interconnection with said reactive ion etching without affecting the integrity of said first insulating layer with protection from said photosensitive polymer.
Claim 12
Dependent Claim
25 words
A method of fabricating an integrated circuit as described in claim 9, wherein said substrate is silicon and said first insulating layer is silicon dioxide.
Claim 13
Dependent Claim
25 words
A method of fabricating an integrated circuit as described in claim 9, wherein said substrate is silicon and said first insulating layer is silicon nitride.
Claim 14
Dependent Claim
18 words
A method of fabricating an integrated circuit as described in claim 9, wherein said photosensitive polymer is polyimide.
Claim 15
Dependent Claim
19 words
A method of fabricating an integrated circuit as described in claim 9, wherein said metal is deposited by sputtering.
Claim 16
Dependent Claim
21 words
A method of fabricating an integrated circuit as described in claim 9, wherein said metal is deposited by chemical vapor deposition.
Claim 17
Dependent Claim
26 words
A method of fabricating an integrated circuit as described in claim 9, wherein said metal is selected from a group consisting of copper, aluminum and tungsten.
Claim 18
Dependent Claim
22 words
A method of fabricating an integrated circuit as described in claim 9, wherein said excess metal is removed by chemical-mechanical polishing technique.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |