US5825783A
Expired / Lapsed
US
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Semiconductor integrated circuit device with large-scale memory and controller embedded on one semiconductor chip and method of testing the device
Assignee: Toshiba Corp
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Filing: 1996-11-27
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Granted: 1998-10-20
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Expires: 2016-11-27
Abstract
Abstract A semiconductor integrated circuit device comprises, on a semiconductor chip, a large-scale memory as a main memory, a controller for controlling at least inputting data from the outside of the chip to the large-scale memory, and outputting data from the large-scale memory to the outside of the chip, and a self-test circuit for testing the large-scale memory. The self-test circuit includes a rewritable EEPROM, into which a self-test sequence is written. The self-test circuit tests the large-scale memory in accordance with the self-test sequence written in the EEPROM.
Inventors
- 👤 Tomomi Momohara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:28
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; H; H10; H10P; H10P74/00; G11C29/12; G11C29/18; G11C29/24; G11C29/36
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
87 words
A semiconductor integrated circuit device comprising: a semiconductor chip; a main memory provided on the chip; a controller provided on said chip for controlling at least inputting data from the outside of said chip to said main memory, and outputting data from said main memory to the outside of said chip; and a self-test circuit provided on said chip and having a memory into which a self-test sequence is written, said self-test circuit testing said main memory in accordance with the self-test sequence written in the memory.
Claim 2
Dependent Claim
87 words
A semiconductor integrated circuit device comprising: a semiconductor chip; a main memory provided on the chip; a controller provided on said chip for controlling at least inputting data from the outside of said chip to said main memory, and outputting data from said main memory to the outside of said chip; and a self-test circuit provided on said chip and having a memory into which a self-test sequence is written, said self-test circuit testing said main memory in accordance with the self-test sequence written in the memory.
Claim 3
Dependent Claim
23 words
The semiconductor integrated circuit device according to claim 1, wherein said memory permits data to be written therein and to be erased therefrom.
Claim 4
Dependent Claim
40 words
The semiconductor integrated circuit device according to claim 1, wherein said self-test circuit obtains a fail address stored in said main memory by testing said main memory, and causes another memory provided on said chip to store the fail address.
Claim 5
Dependent Claim
21 words
The semiconductor integrated circuit device according to claim 3, wherein said another memory is a buffer memory included in said controller.
Claim 6
Dependent Claim
49 words
The semiconductor integrated circuit device according to claim 3, wherein said main memory includes a redundancy circuit, and said self-test circuit includes a self-redundancy control circuit for assigning an address corresponding to the fail address, to said redundancy circuit to thereby save the fail address in said main memory.
Claim 7
Dependent Claim
55 words
The semiconductor integrated circuit device according to claim 5, wherein said redundancy circuit includes a redundancy memory cell array, and a replacement data memory in which address replacement data is written and stored, the replacement data memory causing said redundancy memory cell array to be operable, on the basis of the stored address replacement data.
Claim 8
Dependent Claim
25 words
The semiconductor integrated circuit device according to claim 6, wherein said replacement data memory permits data to be written therein and to be erased therefrom.
Claim 9
Dependent Claim
47 words
The semiconductor integrated circuit device according to claim 7, wherein said redundancy circuit further includes a register for storing redundancy fail address data, and a comparator for comparing the redundancy address data stored in said register with the address replacement data stored in said replacement data memory.
Claim 10
Dependent Claim
54 words
The semiconductor integrated circuit device according to claim 8, wherein said self-redundancy control circuit erases the address replacement data stored in said replacement data memory when said comparator determines that the redundancy address data is not identical to the address replacement data, and again writes the address replacement data into said replacement data memory.
Claim 11
Dependent Claim
54 words
The semiconductor integrated circuit device according to claim 1, further comprising a comparator for comparing test data stored in said memory of said self-test circuit with data output from said main memory, thereby determining whether a memory cell included in said main memory is considered "Pass" or "Fail", and outputting one of determination signals.
Claim 12
Dependent Claim
58 words
The semiconductor integrated circuit device according to claim 10, wherein said memory of said self-test circuit outputs a test address signal to said main memory and said another memory, and said another memory stores the test address signal only when said comparator outputs that one of the determination signals which indicates that the memory cell is considered "Fail".
Claim 13
Dependent Claim
27 words
The semiconductor integrated circuit device according to claim 11, further comprising a monitor line for outputting the output of said comparator to the outside of said chip.
Claim 14
Independent Claim
267 words
A method for testing a semiconductor integrated circuit device having, on a semiconductor chip, at least a main memory; a controller for controlling at least inputting data from the outside of said chip to said main memory, and outputting data from said main memory to the outside of said chip; a rewritable memory different from said main memory, in which the data can be rewritten; a memory different from said main memory and said rewritable memory; a redundancy circuit including a redundancy memory cell array, and a replacement data memory for causing said redundancy memory cell array to be operable on the basis of address replacement data stored therein; a self-test circuit for testing said main memory in accordance with a self-test sequence written in said rewritable memory, and causing said memory to store a fail address included in the main memory and obtained by the test; a self-redundancy control circuit for assigning an address corresponding to the fail address in the main memory, to said redundancy memory cell array of said redundancy circuit in accordance with a self-redundancy control sequence written in said rewritable memory, to thereby save the fail address, the method comprising the steps of: testing at least said controller, said memory, said rewritable memory, said self-test circuit and said self-redundancy on the basis of external test signals output from an external tester; and writing into said rewritable memory a self-test sequence output from said external tester, and testing at least said main memory in accordance with the written self-test sequence on the basis of an internal test signal supplied from said self-test circuit.
Claim 15
Independent Claim
267 words
A method for testing a semiconductor integrated circuit device having, on a semiconductor chip, at least a main memory; a controller for controlling at least inputting data from the outside of said chip to said main memory, and outputting data from said main memory to the outside of said chip; a rewritable memory different from said main memory, in which the data can be rewritten; a memory different from said main memory and said rewritable memory; a redundancy circuit including a redundancy memory cell array, and a replacement data memory for causing said redundancy memory cell array to be operable on the basis of address replacement data stored therein; a self-test circuit for testing said main memory in accordance with a self-test sequence written in said rewritable memory, and causing said memory to store a fail address included in the main memory and obtained by the test; a self-redundancy control circuit for assigning an address corresponding to the fail address in the main memory, to said redundancy memory cell array of said redundancy circuit in accordance with a self-redundancy control sequence written in said rewritable memory, to thereby save the fail address, the method comprising the steps of: testing at least said controller, said memory, said rewritable memory, said self-test circuit and said self-redundancy on the basis of external test signals output from an external tester; and writing into said rewritable memory a self-test sequence output from said external tester, and testing at least said main memory in accordance with the written self-test sequence on the basis of an internal test signal supplied from said self-test circuit.
Claim 16
Dependent Claim
47 words
The method according to claim 13, further comprising the step of writing into said rewritable memory a self-redundancy sequence output from said external tester, and saving the fail address stored in said main memory by means of said self-redundancy circuit in accordance with the written self-redundancy sequence.
Claim 17
Dependent Claim
21 words
The method according to claim 14, wherein the fail address is stored in said memory anytime during self-testing said main memory.
Claim 18
Dependent Claim
83 words
The method according to claim 13, wherein said redundancy circuit further includes a register for storing fail address data, and a comparator for comparing address replacement data stored in said register with address replacement data actually stored in said replacement data memory, the address replacement data stored in said replacement data memory being erased when said comparator determines that the fail address data is not identical to the address replacement data, and the address replacement data being rewritten into said replacement data memory.
Claim 19
Dependent Claim
45 words
The method according to claim 13, wherein an address corresponding to the fail address included in said main memory is assigned to that cell block included in said redundancy memory cell array, which consists of a plurality of rows or columns, thereby performing address replacement.
Claim 20
Independent Claim
110 words
A method for using a semiconductor integrated circuit device having, on a semiconductor chip, at least a main memory; a controller for controlling at least inputting data from the outside of said chip to said main memory, and outputting data from said main memory to the outside of said chip; and a self-test circuit for testing said main memory in accordance with a self-test sequence written in a rewritable memory different from said main memory, the method comprising the steps of: erasing the self-test sequence from said rewritable memory after self-test processing is finished; and using said rewritable memory as a working memory after the self-test sequence is erased therefrom.
Claim 21
Independent Claim
110 words
A method for using a semiconductor integrated circuit device having, on a semiconductor chip, at least a main memory; a controller for controlling at least inputting data from the outside of said chip to said main memory, and outputting data from said main memory to the outside of said chip; and a self-test circuit for testing said main memory in accordance with a self-test sequence written in a rewritable memory different from said main memory, the method comprising the steps of: erasing the self-test sequence from said rewritable memory after self-test processing is finished; and using said rewritable memory as a working memory after the self-test sequence is erased therefrom.
Claim 22
Dependent Claim
80 words
A semiconductor integrated circuit device comprising: a semiconductor chip; a main memory provided on said chip; a calculation circuit provided on said chip for performing at least calculation on the basis of data stored in said main memory; a rewritable memory provided on said chip and different from said main memory; and a self-test circuit provided on said chip for writing a self-test sequence into said rewritable memory, and testing said main memory in accordance with the written self-test sequence.
Claim 23
Dependent Claim
80 words
A semiconductor integrated circuit device comprising: a semiconductor chip; a main memory provided on said chip; a calculation circuit provided on said chip for performing at least calculation on the basis of data stored in said main memory; a rewritable memory provided on said chip and different from said main memory; and a self-test circuit provided on said chip for writing a self-test sequence into said rewritable memory, and testing said main memory in accordance with the written self-test sequence.
Claim 24
Independent Claim
85 words
A method for testing a semiconductor integrated circuit device having, on a semiconductor chip, at least a main memory, a calculation circuit for performing at least calculation on the basis of data stored in said main memory, and a rewritable memory different from said main memory, the method comprising the steps of: testing at least said calculation circuit by means of an external tester; and writing a self-test sequence into said rewritable memory, and testing said main memory in accordance with the written self-test sequence.
Claim 25
Independent Claim
85 words
A method for testing a semiconductor integrated circuit device having, on a semiconductor chip, at least a main memory, a calculation circuit for performing at least calculation on the basis of data stored in said main memory, and a rewritable memory different from said main memory, the method comprising the steps of: testing at least said calculation circuit by means of an external tester; and writing a self-test sequence into said rewritable memory, and testing said main memory in accordance with the written self-test sequence.
References Cited (Backward Citations)
US4970648A
Cited
US5396499A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |