US5822616A
Expired / Lapsed
US
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DMA controller with prefetch cache rechecking in response to memory fetch decision unit's instruction when address comparing unit determines input address and prefetch address coincide
Assignee: Fujitsu Ltd
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Filing: 1996-03-19
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Granted: 1998-10-13
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Expires: 2016-03-19
Abstract
Abstract A computer which can efficiently perform DMA transfer even if the bus on an input/output adapter side is operating at a high speed and the bus on a main memory side is operating at a low speed. In this computer, the DMA controller functions to prefetch the data to the cache from the main memory and is provided with a prefetch address table holding the prefetch address; an address comparing unit which compares the prefetch address and the input address; a hit recheck control unit which judges if there is a hit in the cache again; and a memory fetch decision unit which instructs the hit recheck control unit to perform a hit recheck when the input address is a cache miss (mis-hit) and a comparison of the input address and the prefetch address shows they coincide while makes a read request to the main memory system when it shows they do not coincide.
Inventors
- 👤 Junji Hirooka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:00
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
141 words
A DMA controller provided with a prefetching function, said DMA controller comprising: a prefetch address table holding a prefetch address generated in association with a cache address; an address comparing unit that compares the prefetch address and an input address of a DMA read request; a hit recheck unit performing a hit recheck by comparing the input address to a cached address identifying data loaded in the cache; and a memory fetch unit that, when the input address does not coincide with a cached address, obtains a result from said address comparing unit and: when said address comparing unit determines the input address and the prefetch address coincide, instructs said hit recheck control unit to perform a hit recheck; and when said address comparing unit determines the input address and the prefetch address do not coincide, generates a demand fetch command.
Claim 2
Dependent Claim
141 words
A DMA controller provided with a prefetching function, said DMA controller comprising: a prefetch address table holding a prefetch address generated in association with a cache address; an address comparing unit that compares the prefetch address and an input address of a DMA read request; a hit recheck unit performing a hit recheck by comparing the input address to a cached address identifying data loaded in the cache; and a memory fetch unit that, when the input address does not coincide with a cached address, obtains a result from said address comparing unit and: when said address comparing unit determines the input address and the prefetch address coincide, instructs said hit recheck control unit to perform a hit recheck; and when said address comparing unit determines the input address and the prefetch address do not coincide, generates a demand fetch command.
Claim 3
Dependent Claim
34 words
A DMA controller as set forth in claim 1, wherein said hit recheck control unit performs a hit recheck when a prefetch corresponding to the prefetch address in the prefetch address table has ended.
Claim 4
Dependent Claim
79 words
A DMA controller as set forth in claim 1, further comprising: a memory bus coupling a main memory to the DMA controller, said memory bus being released when a prefetch has ended; and an I/O bus coupling each one of a plurality of I/O adapters to the DMA controller, said I/O bus being exclusively occupied by an input-output unit coupled to one of said I/O adapters from when the input-output unit issues a command until a reply is returned.
Claim 5
Dependent Claim
79 words
A DMA controller as set forth in claim 2, further comprising: a memory bus coupling a main memory to the DMA controller, said memory bus being released when a prefetch has ended; and an I/O bus coupling each one of a plurality of I/O adapters to the DMA controller, said I/O bus being exclusively occupied by an input-output unit coupled to one of said I/O adapters from when the input-output unit issurs a command until a reply is returned.
Claim 6
Dependent Claim
44 words
A DMA controller as set forth in claim 1, further comprising: a plurality of I/O adapters, each of which independently and exclusively accesses a page at a time of a main memory; and wherein said prefetch address table is accessible in units of pages.
Claim 7
Dependent Claim
44 words
A DMA controller as set forth in claim 2, further comprising: a plurality of I/O adapters, each of which independently and exclusively accesses a page at a time of a main memory; and wherein said prefetch address table is accessible in units of pages.
Claim 8
Dependent Claim
44 words
A DMA controller as set forth in claim 3, further comprising: a plurality of I/O adapters, each of which independently and exclusively accesses a page at a time of a main memory; and wherein said prefetch address table is accessible in units of pages.
Claim 9
Dependent Claim
44 words
A DMA controller as set forth in claim 4, further comprising: a plurality of I/O adapters, each of which independently and exclusively accesses a page at a time of a main memory; and wherein said prefetch address table is accessible in units of pages.
Claim 10
Dependent Claim
131 words
A DMA controller for executing data prefetch operations, said DMA controller comprising: a prefetch address table holding a prefetch address identifying data being prefetched to a cache in response to a first DMA read request; an address comparing unit that performs a comparison of the prefetch address to an input address of a second DMA read request and indicates a result thereof when the second DMA read request results in a cache miss in the cache; a memory fetch decision unit generating a hit recheck instruction when the prefetch address and the input address coincide and generating a demand fetch command when the prefetch address and the input address do not coincide; a hit recheck control unit performing a hit recheck upon the cache in response to the hit recheck instruction.
Claim 11
Dependent Claim
131 words
A DMA controller for executing data prefetch operations, said DMA controller comprising: a prefetch address table holding a prefetch address identifying data being prefetched to a cache in response to a first DMA read request; an address comparing unit that performs a comparison of the prefetch address to an input address of a second DMA read request and indicates a result thereof when the second DMA read request results in a cache miss in the cache; a memory fetch decision unit generating a hit recheck instruction when the prefetch address and the input address coincide and generating a demand fetch command when the prefetch address and the input address do not coincide; a hit recheck control unit performing a hit recheck upon the cache in response to the hit recheck instruction.
Claim 12
Dependent Claim
21 words
The DMA controller of claim 9, wherein said hit recheck control unit performs the hit recheck when a prefetch has ended.
Claim 13
Dependent Claim
67 words
The DMA controller of claim 9, wherein the DMA controller is coupled to a main memory system through a memory bus that is released when a prefetch has ended, and the DMA controller is coupled to an I/O adapter through an I/O bus that is exclusively occupied by an input-output unit issuing a transfer command from the issue of the transfer command until a reply is returned.
Claim 14
Dependent Claim
72 words
The DMA controller of claim 9, wherein: said DMA controller is coupled to a plurality of I/O adapters and to a main memory system including a memory accessible in page units; said prefetch address table includes address space accessible in page units; and a first one of the I/O adapters refrains from accessing a page of the page-accessible memory when a second one of the I/O adapters is currently accessing the page.
Claim 15
Dependent Claim
118 words
The DMA controller of claim 9, wherein: said DMA controller connects to a main memory system through a memory bus that is released when a prefetch has ended; said DMA controller is coupled to a plurality of I/O adapters through an I/O bus that is exclusively occupied by an input-output unit issuing a transfer command upon issue of the transfer command until return of a reply; the main memory system includes a memory accessible in page units; said prefetch address table includes address space accessible in page units; and a first one of the I/O adapters refrains from accessing a page of the page-accessible memory when a second one of the I/O adapters is currently accessing the page.
Claim 16
Independent Claim
126 words
A method for performing DMA data transfer from a main memory, said method comprising the steps of: holding a prefetch address generated in response to a first DMA read request; performing a prefetch of data corresponding to the prefetch address from a main memory system to a cache; receiving an input address of a second DMA read request; determining whether the input address generates a cache miss; and when a cache miss is generated, comparing the prefetch address to the input address and performing the following steps: performing a hit recheck when the prefetch address and the input address coincide; and fetching the data indicated by the second DMA data request from the main memory when the prefetch address and the input address do not coincide.
Claim 17
Independent Claim
126 words
A method for performing DMA data transfer from a main memory, said method comprising the steps of: holding a prefetch address generated in response to a first DMA read request; performing a prefetch of data corresponding to the prefetch address from a main memory system to a cache; receiving an input address of a second DMA read request; determining whether the input address generates a cache miss; and when a cache miss is generated, comparing the prefetch address to the input address and performing the following steps: performing a hit recheck when the prefetch address and the input address coincide; and fetching the data indicated by the second DMA data request from the main memory when the prefetch address and the input address do not coincide.
Claim 18
Dependent Claim
21 words
The method of claim 14, wherein the step of performing a hit recheck step is performed when a prefetch has ended.
Claim 19
Dependent Claim
58 words
The method of claim 14, further comprising the steps of: releasing a memory bus coupled to the DMA controller when a prefetch has ended; and refraining from accessing a page of the main memory with a first one of a plurality of I/O adapters when a second one of the plurality of I/O adapters is accessing the page.
Claim 20
Dependent Claim
128 words
A computer-readable medium encoded with a program for executing DMA controller prefetch operations, said program comprising the functions of: holding a prefetch address generated in response to a first DMA read request; performing a prefetch of data corresponding to the prefetch address from a main memory system to a cache; receiving an input address of a second DMA read request; determining whether the input address generates a cache miss; and when a cache miss is generated, comparing the prefetch address to the input address and performing the following steps: performing a hit recheck when the prefetch address and the input address coincide; and fetching the data indicated by the second DMA data request from the main memory when the prefetch address and the input address do not coincide.
Claim 21
Dependent Claim
128 words
A computer-readable medium encoded with a program for executing DMA controller prefetch operations, said program comprising the functions of: holding a prefetch address generated in response to a first DMA read request; performing a prefetch of data corresponding to the prefetch address from a main memory system to a cache; receiving an input address of a second DMA read request; determining whether the input address generates a cache miss; and when a cache miss is generated, comparing the prefetch address to the input address and performing the following steps: performing a hit recheck when the prefetch address and the input address coincide; and fetching the data indicated by the second DMA data request from the main memory when the prefetch address and the input address do not coincide.
Claim 22
Dependent Claim
22 words
The computer-readable medium of claim 17, wherein said hit recheck performing function includes performing said hit recheck when a prefetch has ended.
Claim 23
Dependent Claim
27 words
The DMA controller as set forth in claim 3, wherein said memory bus operates at a low speed; and said I/O bus operates at a high speed.
References Cited (Backward Citations)
JPH02110646A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |