Micro architecture of video core for MPEG-2 decoder

Claim 2

A video decoder core design comprising a layout for hardware which performs at least some MPEG-2 video decoding functions, said video core being used on a first integrated circuit having a first integrated circuit design and a second integrated circuit having a second integrated circuit design, wherein the first and second integrated circuit designs have at least some features not in common; and wherein the MPEG-2 functions performed by the hardware are only inverse scan, inverse quantization, inverse discrete cosine transform, half pel compensation, and merge.

Claim 3

The video decoder core design of claim 1, further comprising an inverse quantization unit which performs at least the inverse quantization function, wherein the inverse quantization unit includes an input path for receiving encoded discrete cosine transform coefficients from a sequence of encoded video data; and an output path for outputting decoded discrete cosine transform coefficients.

Claim 4

The video decoder core design of claim 2, further comprising a quantization matrices unit which provides quantization matrices for use by the inverse quantization unit for performing the inverse quantization function, wherein the quantization matrices unit includes an interface for receiving quantization matrix values from the sequence of encoded video data.

Claim 5

The video decoder core design of claim 3, wherein inverse quantization unit performs an inverse scan function.

Claim 6

The video decoder core design of claim 1, further comprising a plurality of registers which temporarily store values received from a sequence of compressed video data, the values including at least coded block pattern values and half pel compensation values.

Claim 7

The video decoder core design of claim 1, further comprising an inverse discrete cosine transform unit which performs an inverse discrete cosine transformation on discrete cosine transform coefficients, and wherein the inverse discrete cosine transform unit includes an interface for receiving discrete cosine transform coefficients from a source within the video decoder core design.

Claim 8

The video decoder core design of claim 6, wherein the inverse discrete cosine transform unit implements Chen's algorithm.

Claim 9

The video decoder core design of claim 1, further comprising a half pel compensation unit which includes (i) logic and memory for processing four pixel values simultaneously, and (ii) logic and memory for processing a single odd pixel value simultaneously with four other pixel values to perform right half pel averaging.

Claim 10

The video decoder core design of claim 8, wherein the half pel compensation unit processes rows of pixel data from right to left during right half pel averaging.

Claim 11

The video decoder core design of claim 1, further comprising a merge and store unit which merges error correction blocks passing through an inverse discrete cosine transform unit with motion compensation blocks passing through a half pel compensation unit.

Claim 12

The video decoder core design of claim 10, wherein the merge and store unit passes blocks of decoded pixel values outside the video decoder core.

Claim 13

The video decoder core design of claim 1, wherein the core design is stored on a machine readable media.

Claim 14

The video decoder core design of claim 1, wherein the core design includes the following interface paths: (i) a slave CPU interface path for quantization matrix download, (ii) an I/O path for register access, (iii) an input path for coefficient data, (iv) input path for motion compensation, and (v) an output path for decoded samples.

Claim 15

The video decoder design of claim 1, wherein at least one of the first and the second integrated circuit designs includes an audio decoder.

Claim 16

A video decoder core design comprising a layout for hardware which performs at least some MPEG-2 video decoding functions, said video core being used on a first integrated circuit having a first integrated circuit design and a second integrated circuit having a second integrated circuit design, wherein the first and second integrated circuit designs have at least some features not in common, said video decoder core design consists of: means for performing inverse quantization on encoded discrete cosine transform values, and said means for performing inverse quantization is configured to perform an inverse scan function; means for providing quantization matrices for use by the inverse quantization unit in performing the inverse quantization function, and said means for providing quantization matrices also includes matrix interface means for receiving quantization matrix values from a sequence of encoded video data; a plurality of register means which temporarily store control values received from said sequence of encoded video data; means for performing an inverse discrete cosine transformation on discrete cosine transform coefficients, the means for performing the inverse discrete cosine transform includes a transpose ram and an output ram; means for performing half pel compensation and outputting a result of the half pel compensation to an intermediate ram; and means for merging error correction blocks passing through an inverse discrete cosine transform unit with motion compensation blocks passing through a half pel compensation unit.

Claim 17

A video decoder core design comprising a layout for hardware which performs at least some MPEG-2 video decoding functions, said video core being used on a first integrated circuit having a first integrated circuit design and a second integrated circuit having a second integrated circuit design, wherein the first and second integrated circuit designs have at least some features not in common, said video decoder core design consists of: means for performing inverse quantization on encoded discrete cosine transform values, and said means for performing inverse quantization is configured to perform an inverse scan function; means for providing quantization matrices for use by the inverse quantization unit in performing the inverse quantization function, and said means for providing quantization matrices also includes matrix interface means for receiving quantization matrix values from a sequence of encoded video data; a plurality of register means which temporarily store control values received from said sequence of encoded video data; means for performing an inverse discrete cosine transformation on discrete cosine transform coefficients, the means for performing the inverse discrete cosine transform includes a transpose ram and an output ram; means for performing half pel compensation and outputting a result of the half pel compensation to an intermediate ram; and means for merging error correction blocks passing through an inverse discrete cosine transform unit with motion compensation blocks passing through a half pel compensation unit.

Claim 18

The video decoder core design of claim 15, wherein the means for performing inverse quantization includes input means for receiving encoded discrete cosine transform coefficients from the sequence of encoded video data; and output means for outputting decoded discrete cosine transform coefficients.

Claim 19

The video decoder core design of claim 15, wherein the plurality of register means temporarily store values which include at least coded block pattern values and half pel compensation values.

Claim 20

The video decoder core design of claim 15, wherein the means for performing an inverse discrete cosine transformation includes an interface for receiving discrete cosine transform coefficients from a source within the video decoder core design.

Claim 21

The video decoder core design of claim 18, wherein the means for performing an inverse discrete cosine transformation implements Chen's algorithm.

Claim 22

The video decoder core design of claim 15, wherein the means for performing half pel compensation includes (i) logic and memory for processing four pixel values simultaneously, and (ii) logic and memory for processing a single odd pixel value simultaneously with four other pixel values to perform right half pel averaging.

Claim 23

A video decoder circuit core, comprising a layout for hardware which performs at least some MPEG-2 video decoding functions, said video decoder circuit core being used on a first integrated circuit having a first integrated circuit design and a second integrated circuit having a second integrated circuit design, such that the first and second integrated circuit designs have at least some features not in common; a quantization matrices unit that provides quantization matrices for use by an inverse quantization unit for performing the inverse quantization function, the quantization matrices unit includes an interface for receiving quantization matrix values from a sequence of encoded video data, and an inverse quantization unit for performing an inverse scan function; wherein the MPEG-2 functions performed by the hardware are only the inverse scan function, inverse quantization, inverse discrete cosine transform, half pel compensation, and merge.

Claim 24

A video decoder circuit core, comprising a layout for hardware which performs at least some MPEG-2 video decoding functions, said video decoder circuit core being used on a first integrated circuit having a first integrated circuit design and a second integrated circuit having a second integrated circuit design, such that the first and second integrated circuit designs have at least some features not in common; a quantization matrices unit that provides quantization matrices for use by an inverse quantization unit for performing the inverse quantization function, the quantization matrices unit includes an interface for receiving quantization matrix values from a sequence of encoded video data, and an inverse quantization unit for performing an inverse scan function; wherein the MPEG-2 functions performed by the hardware are only the inverse scan function, inverse quantization, inverse discrete cosine transform, half pel compensation, and merge.

Claim 25

The video decoder core circuit design of claim 21, further comprising an inverse quantization unit that performs the inverse quantization function and the inverse scan function, the inverse quantization unit further comprises: an input path for receiving encoded discrete cosine transform coefficients from the sequence of encoded video data; and an output path for outputting decoded discrete cosine transform coefficients.

Claim 26

The video decoder core circuit design of claim 21, further comprising: an inverse discrete cosine transform unit which performs an inverse discrete cosine transformation on discrete cosine transform coefficients, and wherein the inverse discrete cosine transform unit includes an interface for receiving discrete cosine transform coefficients from a source within the video decoder core circuit design.

Claim 27

The video decoder core circuit design of claim 23, wherein the inverse discrete cosine transform unit implements Chen's algorithm.