Apparatus and method for reducing power consumption in microprocessors through selective gating of clock signals

Claim 1

A circuit to reduce the power consumption of a microprocessor, comprising: a phase-locked loop circuit within said microprocessor to produce an internal clock signal from an externally generated clock signal; activity monitor circuitry within said microprocessor to generate an activity signal in response to a low activity operational state of said microprocessor; a clock controller within said microprocessor and connected to said phase-locked loop circuit and said activity monitor circuitry, said clock controller producing a periodic clock gating signal from said internal clock signal and said activity signal; and clock gating circuits within said microprocessor and connected to said phase-locked loop circuit and said clock controller, said clock gating circuits periodically applying said internal clock signal to microprocessor logic circuitry in response to said periodic clock gating signal such that said microprocessor logic circuitry receives a periodically clocked microprocessor clock for ongoing computational operations with reduced power consumption.