US5811706A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synthesizer system utilizing mass storage devices for real time, low latency access of musical instrument digital samples
Assignee: Native Instruments GmbH
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Filing: 1997-05-27
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Granted: 1998-09-22
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Expires: 2017-05-27
Abstract
Abstract A synthesizer system includes a CPU and host memory operating a software routine. The software routine stores a first part of each waveform signal in a sample pool of host memory and provides remaining portions of selected musical sounds from the hard drive to a stream cell array without an audio perceivable delay. The synthesizer system utilizes a caching system which allows low cost, high storage devices to be utilized in an audio synthesizer system. MIDI control signals are provided to an audio processor for selecting appropriate digital waveform signals.
Inventors
- 👤 James E. Van Buskirk
- 👤 Joseph A. Bibbo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:09
CPC Classifications
G; G10; G10H; G10H7/00; G10H7/02; G10H7/002; G10H2240/00; G10H2240/011; G10H2240/046; G10H2240/056; G10H2250/00; G10H2250/541; G10H2250/641
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
161 words
A memory architecture for a digital synthesizer system, the digital synthesizer system including a mass storage device, and a processor, the mass storage device storing a plurality of digital waveform signals, each of the digital waveform signals corresponding to a particular sound of a plurality of sounds, the processor receiving a digital control signal, the digital control signal being indicative of a selected sound of the sounds, the processor generating a digital sound signal at an output in response the digital control signal, the processor providing a first part of the digital waveform signal corresponding to the selected sound to the output followed by a second part of the digital waveform signal corresponding to the selected sound from the mass storage device, the memory architecture comprising: a sample buffer for storing a first part of each of the digital waveform signals; and a stream buffer for temporarily storing the second part of the digital waveform signal corresponding to the selected sound.
Claim 2
Dependent Claim
161 words
A memory architecture for a digital synthesizer system, the digital synthesizer system including a mass storage device, and a processor, the mass storage device storing a plurality of digital waveform signals, each of the digital waveform signals corresponding to a particular sound of a plurality of sounds, the processor receiving a digital control signal, the digital control signal being indicative of a selected sound of the sounds, the processor generating a digital sound signal at an output in response the digital control signal, the processor providing a first part of the digital waveform signal corresponding to the selected sound to the output followed by a second part of the digital waveform signal corresponding to the selected sound from the mass storage device, the memory architecture comprising: a sample buffer for storing a first part of each of the digital waveform signals; and a stream buffer for temporarily storing the second part of the digital waveform signal corresponding to the selected sound.
Claim 3
Dependent Claim
47 words
The memory architecture of claim 1 wherein the stream buffer is comprised of a plurality of stream buffer cells, each stream buffer cell including a stream deck pointer for addressing the first part of the digital waveform signal corresponding to the selected sound in the sample buffer.
Claim 4
Dependent Claim
37 words
The memory architecture of claim 2 wherein each stream buffer cell includes a stream control data pointer for addressing control data associated with the digital waveform signal corresponding to the selected sound stored in the sample buffer.
Claim 5
Dependent Claim
46 words
The memory architecture of claim 3 wherein the sample buffer is comprised of a plurality of sample buffer cells, each sample buffer cell including a sample deck buffer for storing the first part of the digital waveform signal corresponding to a particular sound of the sounds.
Claim 6
Dependent Claim
35 words
The memory architecture of claim 4 wherein each sample buffer cell includes a sample control data buffer for storing control data associated with the digital waveform signal corresponding to the particular sound of the sounds.
Claim 7
Dependent Claim
25 words
The memory architecture of claim 1 wherein the stream buffer is configurable for a plurality of cell sizes and for a plurality of numbers cells.
Claim 8
Dependent Claim
118 words
An audio processor for providing a digital output signal representative of a sound at an output, the audio processor comprising: a mass storage device input for receiving a plurality of digital waveform signals; a sample pool for storing a first part of the digital waveform signals; a stream buffer; a stream engine coupled to the mass storage device input and to the stream buffer, the stream engine providing a second part of the digital waveform signals from the mass storage device input to the stream buffer; and a synthesizer engine coupled to the stream buffer and the output, wherein the synthesizer engine provides the second part of the digital waveform signals from the stream buffer to the output.
Claim 9
Dependent Claim
118 words
An audio processor for providing a digital output signal representative of a sound at an output, the audio processor comprising: a mass storage device input for receiving a plurality of digital waveform signals; a sample pool for storing a first part of the digital waveform signals; a stream buffer; a stream engine coupled to the mass storage device input and to the stream buffer, the stream engine providing a second part of the digital waveform signals from the mass storage device input to the stream buffer; and a synthesizer engine coupled to the stream buffer and the output, wherein the synthesizer engine provides the second part of the digital waveform signals from the stream buffer to the output.
Claim 10
Dependent Claim
19 words
The audio processor of claim 7 wherein the stream buffer and synchronizer engine are configured on a computer platform.
Claim 11
Dependent Claim
24 words
The audio processor of claim 8 wherein a solid state host memory of the computer platform includes the stream buffer and the sample pool.
Claim 12
Dependent Claim
22 words
The audio processor of claim 9 wherein the computer platform includes a hard disk drive coupled to the mass storage device input.
Claim 13
Dependent Claim
29 words
The audio processor of claim 7 wherein the stream buffer is comprised of a plurality of cells, the stream buffer being configurable to include a particular number of cells.
Claim 14
Dependent Claim
18 words
The audio processor of claim 11 wherein the plurality of cells are configurable to be a particular size.
Claim 15
Dependent Claim
38 words
The audio processor of claim 7 further comprising: a control processor coupled to the stream engine and the synthesizer engine, the control processor causing the stream engine to select particular waveform signals for placement in the stream buffer.
Claim 16
Dependent Claim
32 words
The audio processor of claim 13 wherein the control processor provides a stop flag to the stream buffer to prevent the synthesizer engine from providing a particular waveform signal to the output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-21 | 2002-03-23 | 2002-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-21 | 2006-03-23 | 2006-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-21 | 2010-03-23 | 2010-09-22 | $7700.00 | Window Closed / Lapsed |