Abstract A dual level transistor integrated circuit and a fabrication technique for making the integrated circuit. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed upon a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate. The integrated circuit further includes a first transistor. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. A first local substrate is formed on an upper surface of the first inter-substrate dielectric. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.
A local substrate for a multi-level integrated circuit, wherein said local substrate comprises polycrystalline silicon formed on a first transistor level of said integrated circuit, said polycrystalline silicon having an average grain size greater than approximately 3000 angstroms, and further wherein said local substrate is suitable for forming a second transistor level of said integrated circuit such that said second transistor level is vertically displaced with respect to said first transistor level.
Claim 2
Dependent Claim
72 words
A local substrate for a multi-level integrated circuit, wherein said local substrate comprises polycrystalline silicon formed on a first transistor level of said integrated circuit, said polycrystalline silicon having an average grain size greater than approximately 3000 angstroms, and further wherein said local substrate is suitable for forming a second transistor level of said integrated circuit such that said second transistor level is vertically displaced with respect to said first transistor level.
Claim 3
Dependent Claim
27 words
The local substrate of claim 1 wherein said first transistor level includes a first transistor and an inter-substrate dielectric isolating said first transistor from said local substrate.
Claim 4
Dependent Claim
30 words
The local substrate of claim 2 wherein a thickness of said inter-substrate dielectric comprises an oxide, and wherein a thickness of said inter-substrate dielectric is approximately 0.5 to 15.0 microns.
Claim 5
Dependent Claim
19 words
The local substrate of claim 1 wherein a thickness of said local substrate is approximately 1 to 8 microns.
Claim 6
Dependent Claim
39 words
The local substrate of claim 1 wherein said local substrate further includes a second transistor formed upon said second transistor level such that said second transistor is vertically displaced from a first transistor formed upon said first transistor level.
Claim 7
Dependent Claim
31 words
The local substrate of claim 5 wherein a lateral separation between said first transistor and said second transistor is less than approximately 10% of a lateral dimension of said first transistor.