US5805808A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Real time parser for data packets in a communications network
Assignee: Extreme Networks Inc
•
Filing: 1997-04-09
•
Granted: 1998-09-08
•
Expires: 2017-04-09
Abstract
Abstract A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.
Inventors
- 👤 Santosh K. Hasani
- 👤 Satish L. Rege
- 👤 Mark F. Kempf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:29
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; H; H04; H04L; H04L45/00; H04L45/74; H04L45/745; H04L45/7453; H04L9/00; H04L9/40; H04L69/00; H04L69/22
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
199 words
A parser for use in a station on a computer network, said station receiving a first packet from the computer network, said first packet being a stream of bits, said bits arranged in a plurality of fields of said first packet, said parser for interpreting said bits of said first packet, comprising: a station memory; a set of logic circuits implemented in a computer chip; a memory interacting with said computer chip, said memory providing first data to said set of logic circuits; means for reading said bits from said plurality of fields of said first packet into said set of logic circuits, said bits providing second data to said set of logic circuits; means, responsive to said first data and said second data, to create a forwarding vector to be used by said logic circuits to determine a destination for the first packet and to forward said packet to the station if the packet has a destination address which matches a host destination address and to discard said packet if said destination address does not match said host destination address, wherein the station either forwards or discards the packet without reading the entire packet into said station memory.
Claim 2
Dependent Claim
199 words
A parser for use in a station on a computer network, said station receiving a first packet from the computer network, said first packet being a stream of bits, said bits arranged in a plurality of fields of said first packet, said parser for interpreting said bits of said first packet, comprising: a station memory; a set of logic circuits implemented in a computer chip; a memory interacting with said computer chip, said memory providing first data to said set of logic circuits; means for reading said bits from said plurality of fields of said first packet into said set of logic circuits, said bits providing second data to said set of logic circuits; means, responsive to said first data and said second data, to create a forwarding vector to be used by said logic circuits to determine a destination for the first packet and to forward said packet to the station if the packet has a destination address which matches a host destination address and to discard said packet if said destination address does not match said host destination address, wherein the station either forwards or discards the packet without reading the entire packet into said station memory.
Claim 3
Dependent Claim
17 words
The apparatus as in claim 1 wherein said computer chip is an application specific integrated circuit (ASIC).
Claim 4
Dependent Claim
16 words
The apparatus as in claim 1 wherein said memory further comprises a contentent addressable memory (CAM).
Claim 5
Dependent Claim
19 words
The apparatus as in claim 3 wherein said content addressable memory is a static random access memory chip (SRAM).
Claim 6
Dependent Claim
28 words
The apparatus as in claim 1 further comprising: means for writing said first data to said memory after parsing said first packet and before parsing a second packet.
Claim 7
Dependent Claim
46 words
The apparatus as in claim 5 further comprising: an adapter manager microprocessor; means for said adapter manager microprocessor to write at least some of said first data to said memory dynamically after parsing for said first packet is complete and before beginning parsing said second packet.
Claim 8
Dependent Claim
61 words
The apparatus as in claim 1 further comprising: packet memory for storing said first packet; means for determining that a particular packet is to be discarded and not stored in packet memory; means, responsive to a determination that said particular packet is to be discharged, for asserting an electrical signal to prevent storage of said particular packet in said packet memory.
Claim 9
Dependent Claim
34 words
The apparatus as in claim 1 wherein said forwarding vector further comprises a parity check field, a discard field, a destination field, a packet type field, a user field and a recipient process field.
Claim 10
Dependent Claim
189 words
A network adapter in a computer network, the network adapter receiving a first packet from the computer network, the first packet having a plurality of fields, the plurality of fields including packet header fields and a plurality of other fields, the header fields containing destination address data, the network adapter comprising: an adapter memory; a parser database providing network data; a parser to examine the header fields of the first data packet and to compare the contents of each said header field of the first data packet with said network data in said parser database, said parser to create a forwarding vector in response to the contents of the examined header fields and said network data, said forwarding vector to be used by the network adapter to determine a destination for the first packet and to forward said packet to a host if the packet has a destination address which matches a host destination address and to discard said packet if said destination address does not match said host destination address, wherein the adapter either forwards or discards the packet without reading the entire packet into said adapter memory.
Claim 11
Dependent Claim
189 words
A network adapter in a computer network, the network adapter receiving a first packet from the computer network, the first packet having a plurality of fields, the plurality of fields including packet header fields and a plurality of other fields, the header fields containing destination address data, the network adapter comprising: an adapter memory; a parser database providing network data; a parser to examine the header fields of the first data packet and to compare the contents of each said header field of the first data packet with said network data in said parser database, said parser to create a forwarding vector in response to the contents of the examined header fields and said network data, said forwarding vector to be used by the network adapter to determine a destination for the first packet and to forward said packet to a host if the packet has a destination address which matches a host destination address and to discard said packet if said destination address does not match said host destination address, wherein the adapter either forwards or discards the packet without reading the entire packet into said adapter memory.
Claim 12
Dependent Claim
23 words
The network adapter of claim 9, further comprising: a packet memory controller using said forwarding vector to control disposition of the first packet.
Claim 13
Dependent Claim
33 words
The network adapter of claim 9, wherein the first packet is longer than 512 bytes and is stored in a plurality of pages and a forwarding vector is generated for each said page.
Claim 14
Dependent Claim
16 words
The network adapter of claim 9, wherein said parser database is dynamically changed by said host.
Claim 15
Dependent Claim
57 words
The network adapter of claim 9, wherein said first packet includes a destination address field, said destination address field having a plurality of bit masks, said parser using a logical OR operation on said plurality of bit masks, a resultant of "zero" of said logical OR operation indicating a valid destination address in said destination address field.
References Cited (Backward Citations)
US4905138A
Cited
US4941089A
Cited
US5067104A
Cited
US4839891A
Cited
US4991133A
Cited
US4979167A
Cited
US5056058A
Cited
US5249292A
Cited
US5058110A
Cited
US5235644A
Cited
US5228083A
Cited
US5361353A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-07 | 2002-03-09 | 2002-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-07 | 2006-03-09 | 2006-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-07 | 2010-03-09 | 2010-09-08 | $7700.00 | Window Closed / Lapsed |