US5799208A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for data communication between universal asynchronous receiver/transmitter (UART) modules and transceivers in a chip set by selectively connecting a common bus between multiplexer/demultiplexer units
Assignee: United Microelectronics Corp
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Filing: 1996-04-03
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Granted: 1998-08-25
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Expires: 2016-04-03
Abstract
Abstract An apparatus that provides data communication between universal asynchronous receiver/transmitter (UART) modules on a first IC chip of a chip set and associated transceivers on a second IC chip of the same chip set. The apparatus includes a first multiplexer/demultiplexer unit coupled by first buses to the UART modules, and a second multiplexer/demultiplexer unit coupled by second buses to the transceivers. A common bus is interconnected between the first multiplexer/demultiplexer unit and the second multiplexer/demultiplexer unit. A control unit selectively connects the common bus to one of the first buses and one of the second buses so as to connect one of the UART modules in the first IC chip to the associated transceiver in the second IC chip.
Inventors
- 👤 Chyou-Hsiung Hwang
- 👤 Cheng-Wang Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:54
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
179 words
In an apparatus in which data communication is provided between a plurality of universal asynchronous receiver/transmitter (UART) modules in a first IC chip and a plurality of transceivers in a second IC chip, the transceivers being connected to a plurality of RS-232 interfaces, the improvement comprising: (a) a first multiplexer/demultiplexer unit and a plurality of first bi-directional buses coupling said first multiplexer/demultiplexer unit to the plurality of UART modules; (b) a second multiplexer/demultiplexer unit and a plurality of second bi-directional buses coupling said second multiplexer/demultiplexer unit to the plurality of transceivers; (c) a bi-directional common bus, coupled between said first multiplexer/demultiplexer unit and said second multiplexer/demultiplexer unit, for providing data communication between the plurality of UART modules and the plurality of transceivers; and (d) a control unit for selectively connecting said common bus to a selected one of said plurality of first buses and to one of said plurality of second buses, so as to connect one of the plurality of UART modules in the first IC chip to a selected one associated transceiver in the second IC chip.
Claim 2
Dependent Claim
179 words
In an apparatus in which data communication is provided between a plurality of universal asynchronous receiver/transmitter (UART) modules in a first IC chip and a plurality of transceivers in a second IC chip, the transceivers being connected to a plurality of RS-232 interfaces, the improvement comprising: (a) a first multiplexer/demultiplexer unit and a plurality of first bi-directional buses coupling said first multiplexer/demultiplexer unit to the plurality of UART modules; (b) a second multiplexer/demultiplexer unit and a plurality of second bi-directional buses coupling said second multiplexer/demultiplexer unit to the plurality of transceivers; (c) a bi-directional common bus, coupled between said first multiplexer/demultiplexer unit and said second multiplexer/demultiplexer unit, for providing data communication between the plurality of UART modules and the plurality of transceivers; and (d) a control unit for selectively connecting said common bus to a selected one of said plurality of first buses and to one of said plurality of second buses, so as to connect one of the plurality of UART modules in the first IC chip to a selected one associated transceiver in the second IC chip.
Claim 3
Dependent Claim
23 words
An apparatus as claimed in claim 1, wherein said first multiplexer/demultiplexer unit and said control unit are incorporated in the first IC chip.
Claim 4
Dependent Claim
19 words
An apparatus as claimed in claim 1, wherein said second multiplexer/demultiplexer unit is incorporated in the second IC chip.
Claim 5
Dependent Claim
45 words
An apparatus as claimed in claim 1, wherein the common bus includes a number of signal lines that is the same as a number of signal lines included in the largest of the plurality of first bi-directional buses and the plurality of second bi-directional buses.
Claim 6
Dependent Claim
181 words
A data communication apparatus for communication among a plurality of computers, comprising: a plurality of interfaces, each for connection to a respective one of the computers; a first IC chip having a plurality of universal asynchronous receiver/transmitter (UART) modules; a second IC chip having a plurality of transceivers connected to the interfaces; a first multiplexer/demultiplexer unit and a plurality of first bi-directional buses coupling said first multiplexer/demultiplexer unit to the plurality of UART modules; a second multiplexer/demultiplexer unit and a plurality of second bi-directional buses coupling said second multiplexer/demultiplexer unit to the plurality of transceivers; a bi-directional common bus, coupled between said first multiplexer/demultiplexer unit and said second multiplexer/demultiplexer unit, for providing data communication between the plurality of UART modules and the plurality of transceivers; and a control unit for selectively connecting said common bus to one of said plurality of first buses and to one of said plurality of second buses, so as to connect a selected one of the plurality of UART modules in the first IC chip to a selected one associated transceiver in the second IC chip.
Claim 7
Dependent Claim
181 words
A data communication apparatus for communication among a plurality of computers, comprising: a plurality of interfaces, each for connection to a respective one of the computers; a first IC chip having a plurality of universal asynchronous receiver/transmitter (UART) modules; a second IC chip having a plurality of transceivers connected to the interfaces; a first multiplexer/demultiplexer unit and a plurality of first bi-directional buses coupling said first multiplexer/demultiplexer unit to the plurality of UART modules; a second multiplexer/demultiplexer unit and a plurality of second bi-directional buses coupling said second multiplexer/demultiplexer unit to the plurality of transceivers; a bi-directional common bus, coupled between said first multiplexer/demultiplexer unit and said second multiplexer/demultiplexer unit, for providing data communication between the plurality of UART modules and the plurality of transceivers; and a control unit for selectively connecting said common bus to one of said plurality of first buses and to one of said plurality of second buses, so as to connect a selected one of the plurality of UART modules in the first IC chip to a selected one associated transceiver in the second IC chip.
Claim 8
Dependent Claim
23 words
An apparatus as claimed in claim 5, wherein said first multiplexer/demultiplexer unit and said control unit are incorporated in the first IC chip.
Claim 9
Dependent Claim
19 words
An apparatus as claimed in claim 5, wherein said second multiplexer/demultiplexer unit is incorporated in the second IC chip.
Claim 10
Dependent Claim
13 words
An apparatus as claimed in claim 5, wherein said interfaces are RS-232 interfaces.
Claim 11
Dependent Claim
38 words
An apparatus as claimed in claim 5, wherein each of said interfaces is connected to a respective one of said transceivers by a bus that includes at least eight signal lines for carrying at least eight respective signals.
Claim 12
Dependent Claim
45 words
An apparatus as claimed in claim 5, wherein the common bus includes a number of signal lines that is the same as a number of signal lines included in the largest of the plurality of first bi-directional buses and the plurality of second bi-directional buses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-24 | 2002-02-23 | 2002-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-24 | 2006-02-23 | 2006-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-24 | 2010-02-23 | 2010-08-25 | $7700.00 | Window Closed / Lapsed |