Code sequence generator in a CDMA modem

Claim 1

A code sequence generator apparatus which generates a plurality of spreading code sequences including a master spreading code sequence, the plurality of spreading code sequences having relatively low mutual cross correlation, and having a predetermined mutual code phase relationship, said code sequence generator apparatus comprising: a clock generator means for generating a clock signal a linear feedback shift register (LFSR), responsive to the clock signal and having a plurality of stages including a first stage and a last stage, each stage defining a respective tap, each tap producing a tap signal; wherein a predetermined group of the tap signals including the tap signal of the last stage are applied to logic circuitry which combines the tap signals to produce a feedback spreading-code signal, said feedback spreading-code signal being applied as an input signal to the first stage of the LFSR; first memory means for storing a plurality of spreading-code seeds, each spreading-code seed comprising a set of spreading-code sequence bit values, and said first memory being connected to the LFSR and being responsive to a load signal for transferring each one of a predetermined set of the spreading-code sequence bit values of a selected one of the plurality of spreading-code seed into a respective one of the shift register stages of the LSFR; code generator controller means for selecting one of the plurality of spreading-code seeds to determine the plurality of spreading code sequences and for providing the load signal indicating said one spreading-code seed; wherein said LSFR is responsive to the clock signal to sequentially transfer each respective tap signal from one stage to the next stage, from the first stage to the last stage and for transferring the feedback spreading-code value to the first stage, and each successive one of the tap values of the last stage defines the master spreading code sequence second memory means being responsive to the clock signal for providing a repetitive even code sequence, said even code sequence having relatively low cross correlation with the master spreading sequence and having an even number of chip spreading values; a plurality of cascade connected feedforward means, coupled to receive the master spreading code sequence, for providing a plurality of code sequences, each code sequence being a distinct spreading code sequence of said plurality of spreading code sequences, said feedforward means being responsive to the clock signal, to provide a plurality of spreading code sequences; and a plurality code sequence combining means, each code sequence combining means for combining respective spreading code sequence with said even code sequence to produce a plurality of relatively long spreading code.