US5796672A
Expired / Lapsed
US
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Method and circuit for routing data to registers in an integrated circuit
Assignee: Texas Instruments Inc
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Filing: 1997-04-24
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Granted: 1998-08-18
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Expires: 2017-04-24
Abstract
Abstract A method and circuit for routing data to registers in an integrated circuit is disclosed. The circuit comprises an I/O port (100) for receiving data and address signals, and a plurality of distributed memory modules (200-900) having registers (210-217). Each memory module is associated with and located adjacent to a circuit functional block. All of the memory modules (200-900) are connected to the I/O port (100) via a single data bus (40).
Inventors
- 👤 Jeanne K. Pitz
- 👤 Fredrick W. Trafton
- 👤 Richard C. Pierson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:49
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/066
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
140 words
An integrated circuit for routing data to and from a plurality of registers, the circuit comprising: an I/O port for receiving data and address signals having a first register address decoder; and a plurality of distributed memory modules, each memory module being connected to the I/O port via a data bus, each memory module being connected to and located adjacent to a corresponding one of a plurality of functional blocks; wherein said first register address decoder receives the address signal and transmits a register address signal to the selected memory module; and wherein each memory module further comprises a second register address decoder, for receiving the register address signal from the first register address decoder and for transmitting a register select signal to a selected one of the registers of the memory module in response to the register address signal.
Claim 2
Dependent Claim
140 words
An integrated circuit for routing data to and from a plurality of registers, the circuit comprising: an I/O port for receiving data and address signals having a first register address decoder; and a plurality of distributed memory modules, each memory module being connected to the I/O port via a data bus, each memory module being connected to and located adjacent to a corresponding one of a plurality of functional blocks; wherein said first register address decoder receives the address signal and transmits a register address signal to the selected memory module; and wherein each memory module further comprises a second register address decoder, for receiving the register address signal from the first register address decoder and for transmitting a register select signal to a selected one of the registers of the memory module in response to the register address signal.
Claim 3
Dependent Claim
44 words
The circuit of claim 1, wherein the I/O port comprises a module select decoder for receiving the address signal, for selecting one of the memory modules in response to the address signal, and for transmitting a module select signal to the selected memory module.
Claim 4
Dependent Claim
51 words
The circuit of claim 1, wherein the data signal received by the I/O port comprises a serial data signal, and wherein the I/O port comprises a serial-to-parallel converter, for receiving the data signal and for transmitting a parallel output data signal on the data bus in response to the data signal.
Claim 5
Dependent Claim
27 words
The circuit of claim 1, further comprising an address bus for transmitting the register address signal from the first register address decoder to the selected memory module.
Claim 6
Dependent Claim
18 words
The circuit of claim 1, wherein each memory module has at least one of the plurality of registers.
Claim 7
Dependent Claim
118 words
An integrated circuit formed on a single substrate, comprising: a plurality of circuit functional blocks; an I/O port for receiving address and data signals, and for generating module select, register address, and output data signals; a memory module associated with and located adjacent to a selected one of the circuit functional blocks; a data bus connected to the I/O port and the memory module, for transmitting the output data signal to the memory module; an address bus connected to the I/O port and the memory module, for transmitting the register address signal to the memory module; and a plurality of memory output lines for transmitting memory output signals from the memory module to the selected circuit functional block.
Claim 8
Dependent Claim
118 words
An integrated circuit formed on a single substrate, comprising: a plurality of circuit functional blocks; an I/O port for receiving address and data signals, and for generating module select, register address, and output data signals; a memory module associated with and located adjacent to a selected one of the circuit functional blocks; a data bus connected to the I/O port and the memory module, for transmitting the output data signal to the memory module; an address bus connected to the I/O port and the memory module, for transmitting the register address signal to the memory module; and a plurality of memory output lines for transmitting memory output signals from the memory module to the selected circuit functional block.
Claim 9
Dependent Claim
31 words
The integrated circuit of claim 6, further comprising a module select line connected to the I/O port and the memory module, for transmitting the module select signal to the memory module.
Claim 10
Dependent Claim
37 words
The integrated circuit of claim 6, wherein the memory module comprises a plurality of registers connected to the data bus, for receiving the output data signal and for storing data in response to the output data signal.
Claim 11
Dependent Claim
19 words
The integrated circuit of claim 8, wherein each register is connected to a plurality of the memory output lines.
Claim 12
Dependent Claim
35 words
The integrated circuit of claim 6, wherein the I/O port comprises an address decoder, for receiving the address signal and for generating the module select and register address signals in response to the address signal.
Claim 13
Dependent Claim
45 words
The integrated circuit of claim 6, wherein the I/O port comprises a shift register, for receiving the data signal and for generating the output data signal, the data signal comprising a serial data signal and the output data signal comprising a plurality of parallel bits.
Claim 14
Dependent Claim
47 words
The integrated circuit of claim 6, wherein the memory module comprises a register address decoder, for receiving the register address signal, for selecting one of the plurality of registers in response to the register address signal, and for transmitting a register select signal to the selected register.
Claim 15
Independent Claim
184 words
A method for distributing data to a register in an integrated circuit, the integrated circuit having a plurality of functional blocks, the method comprising the steps of: receiving at an I/O port an input data signal and an input address signal; generating at the I/O port an output data signal in response to the input data signal; generating at the I/O port an output address signal in response to the input address signal; transmitting the output data signal and the output address signal to the memory modules, each memory module being associated with and proximate to a selected one of the functional blocks; receiving at the memory modules the output address signal; selecting one of the plurality of memory modules in response to the input data signal, the selected memory module including the register; transmitting a module select signal to the selected memory module; selecting the register in response to the output address signal and the module select signal; and receiving at the register the output data signal and storing at the register a plurality of bits in response to the output data signal.
Claim 16
Independent Claim
184 words
A method for distributing data to a register in an integrated circuit, the integrated circuit having a plurality of functional blocks, the method comprising the steps of: receiving at an I/O port an input data signal and an input address signal; generating at the I/O port an output data signal in response to the input data signal; generating at the I/O port an output address signal in response to the input address signal; transmitting the output data signal and the output address signal to the memory modules, each memory module being associated with and proximate to a selected one of the functional blocks; receiving at the memory modules the output address signal; selecting one of the plurality of memory modules in response to the input data signal, the selected memory module including the register; transmitting a module select signal to the selected memory module; selecting the register in response to the output address signal and the module select signal; and receiving at the register the output data signal and storing at the register a plurality of bits in response to the output data signal.
Claim 17
Dependent Claim
15 words
The method of claim 13, wherein the output data signal comprises a parallel data signal.
Claim 18
Dependent Claim
15 words
The method of claim 13, wherein the input data signal comprises a serial data signal.
Claim 19
Dependent Claim
15 words
The method of claim 13, wherein the output address signal comprises a parallel data signal.
Claim 20
Dependent Claim
15 words
The method of claim 13, wherein the input address signal comprises a serial data signal.
Claim 21
Dependent Claim
23 words
The method of claim 13, further comprising the step of transmitting a memory output signal from the register to a selected functional block.
References Cited (Backward Citations)
US5146577A
Cited
US5430859A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-17 | 2002-02-16 | 2002-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-17 | 2006-02-16 | 2006-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-17 | 2010-02-16 | 2010-08-18 | $7700.00 | Window Closed / Lapsed |