Semiconductor memory device having divided word line

Claim 2

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; and a plurality of main word lines extending through said plurality of memory array blocks, wherein each of said plurality of memory cells includes a memory transistor and a memory capacitor; each of said plurality of memory array blocks includes: a plurality of sub-word lines connected to said plurality of memory cells in said memory array block, and connected to said plurality of main word lines, and a cell plate divided correspondingly to said plurality of memory array blocks, and forming a common electrode of said memory capacitors of said plurality of memory cells in each of said memory array blocks; and said semiconductor memory device further comprises: a cell plate potential supply line for supplying a cell plate potential to said cell plates in said plurality of memory array blocks, and a plurality of cut-off means arranged between said cell plates in said plurality of memory array blocks and said cell plate potential supply line, respectively, and provided for cutting off the supply of said cell plate potential to a defective one among said memory array blocks.

Claim 3

The semiconductor memory device according to claim 1, wherein all or a part of said plurality of cut-off means are formed of fuse elements.

Claim 4

The semiconductor memory device according to claim 1, wherein all or a part of said plurality of cut-off means are formed of transistor elements.

Claim 5

The semiconductor memory device according to claim 3, wherein the operation of said transistor elements is controlled by a signal used for selecting said memory array block.

Claim 6

The semiconductor memory device according to claim 3, wherein the operation of said transistor element is controlled by a signal indicative of a result of determination whether the corresponding memory array block is defective or not.

Claim 7

The semiconductor memory device according to claim 1, wherein a column address is input after input of a row address, and said plurality of sub-word lines are activated selectively in all of said plurality of memory array blocks in relation to the input of the row address.

Claim 8

The semiconductor memory device according to claim 1, wherein a row address and a column address are input simultaneously, and said plurality of sub-word lines are activated selectively in the selected memory array block among said plurality of memory array blocks in relation to input of the row address and the column address.

Claim 9

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; a plurality of main word lines extending through said plurality of memory array blocks; and a plurality of bit line pairs arranged in each of said plurality of memory array blocks along a direction crossing said main word lines and connected to said plurality of memory cells in the corresponding memory array blocks, wherein each of said plurality of memory array blocks includes a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines; and said semiconductor memory device further comprises: a plurality of equalizer means provided correspondingly to said plurality of bit line pairs and each provided for equalizing potentials on the corresponding bit line pair; an equalization control signal main supply line arranged along said plurality of memory array blocks and provided for supplying an equalization control signal for controlling said plurality of equalizer means; a plurality of equalization control signal sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each provided for transmitting said equalization control signal supplied from said equalization control signal main supply line to each of said equalizer means equalizing said plurality of bit line pairs in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of equalization control signal sub-supply lines, respectively, and being operable to cut off the supply of said equalization control signal from said equalization control signal main supply line to said equalization control signal sub-supply line corresponding to defective one among said memory array blocks.

Claim 10

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; a plurality of main word lines extending through said plurality of memory array blocks; and a plurality of bit line pairs arranged in each of said plurality of memory array blocks along a direction crossing said main word lines and connected to said plurality of memory cells in the corresponding memory array blocks, wherein each of said plurality of memory array blocks includes a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines; and said semiconductor memory device further comprises: a plurality of equalizer means provided correspondingly to said plurality of bit line pairs and each provided for equalizing potentials on the corresponding bit line pair; an equalization control signal main supply line arranged along said plurality of memory array blocks and provided for supplying an equalization control signal for controlling said plurality of equalizer means; a plurality of equalization control signal sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each provided for transmitting said equalization control signal supplied from said equalization control signal main supply line to each of said equalizer means equalizing said plurality of bit line pairs in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of equalization control signal sub-supply lines, respectively, and being operable to cut off the supply of said equalization control signal from said equalization control signal main supply line to said equalization control signal sub-supply line corresponding to defective one among said memory array blocks.

Claim 11

The semiconductor memory device according to claim 8, wherein all of a part of said cut-off means is formed of logic means.

Claim 12

The semiconductor memory device according to claim 9, wherein said logic means receives a signal sent from the corresponding signal supply line as well as a signal indicative of a result of determination whether the corresponding memory array block is defective or not, and is controlled in response to these signals.

Claim 13

The semiconductor memory device according to claim 8, wherein a column address is input after input of a row address, and said plurality of sub-word lines are activated selectively in all of said plurality of memory array blocks in relation to input of the row address.

Claim 14

The semiconductor memory device according to claim 8, wherein a row address and a column address are input simultaneously, and said plurality of sub-word lines are activated selectively in the selected memory array block among said plurality of memory array blocks in relation to input of the row address and the column address.

Claim 15

The semiconductor memory device according to claim 8, further comprising: a plurality of sense amplifier means provided correspondingly to said plurality of bit line pairs, respectively, and each being operable to sense and amplify a potential difference on the corresponding bit line pair; and a plurality of switching means provided correspondingly to respective ones of said plurality of bit line pairs, between said memory cell array and said plurality of sense amplifier means, and each provided for switching the state of connection between the corresponding said bit line pair and said sense amplifier means, wherein said plurality of equalizer means are provided between said memory cell array and said plurality of switching means.

Claim 16

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; a plurality of main word lines extending through said plurality of memory array blocks; and a plurality of bit line pairs arranged in each of said plurality of memory array blocks along a direction crossing said main word lines and connected to said plurality of memory cells in the corresponding memory array blocks, wherein each of said plurality of memory array blocks includes a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines; and said semiconductor memory device further comprises: a plurality of sense amplifier means provided correspondingly to said plurality of bit line pairs and each being operable to sense and amplify a potential difference on the corresponding bit line pair; a plurality of switching means arranged between the corresponding bit line pairs and said sense amplifier means, respectively, and being operable to switch a state of connection between them; a switching control signal main supply line arranged along said plurality of memory array blocks and being operable to supply a switching control signal for controlling said plurality of switching means; a plurality of switching control signal sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each being operable to transmit said switching control signal supplied from said switching control signal main supply line to said plurality of switching means corresponding to said plurality of bit line pairs in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of switching control signal sub-supply lines, respectively, and each being operable to cut off the supply of said switching control signal sent from said switching control signal main supply line to said switching control signal sub-supply line corresponding to defective one among said memory array blocks.

Claim 17

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; a plurality of main word lines extending through said plurality of memory array blocks; and a plurality of bit line pairs arranged in each of said plurality of memory array blocks along a direction crossing said main word lines and connected to said plurality of memory cells in the corresponding memory array blocks, wherein each of said plurality of memory array blocks includes a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines; and said semiconductor memory device further comprises: a plurality of sense amplifier means provided correspondingly to said plurality of bit line pairs and each being operable to sense and amplify a potential difference on the corresponding bit line pair; a plurality of switching means arranged between the corresponding bit line pairs and said sense amplifier means, respectively, and being operable to switch a state of connection between them; a switching control signal main supply line arranged along said plurality of memory array blocks and being operable to supply a switching control signal for controlling said plurality of switching means; a plurality of switching control signal sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each being operable to transmit said switching control signal supplied from said switching control signal main supply line to said plurality of switching means corresponding to said plurality of bit line pairs in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of switching control signal sub-supply lines, respectively, and each being operable to cut off the supply of said switching control signal sent from said switching control signal main supply line to said switching control signal sub-supply line corresponding to defective one among said memory array blocks.

Claim 18

The semiconductor memory device according to claim 14, wherein a column address is input after input of a row address, and said plurality of sub-word lines are activated selectively in all of said plurality of memory array blocks in relation to input of the row address.

Claim 19

The semiconductor memory device according to claim 14, wherein a row address and a column address are input simultaneously and said plurality of sub-word lines are activated selectively in the selected memory array block among said plurality of memory array blocks in relation to input of the row address and the column address.

Claim 20

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; a plurality of main word lines extending through said plurality of memory array blocks; a plurality of bit line pairs arranged in each of said plurality of memory array blocks along a direction crossing said main word lines and connected to said plurality of memory cells in the corresponding memory array blocks, wherein each of said plurality of memory array blocks includes a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines; said semiconductor memory device further comprises: a plurality of equalizer means provided correspondingly to said plurality of bit line pairs and each provided for equalizing potentials on the corresponding bit line pair; an equalization potential main supply line arranged along said plurality of memory array blocks and being provided for supplying an equalization potential for equalizing said plurality of bit line pairs; a plurality of equalization potential sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each being provided for transmitting said equalization potential supplied from said equalization potential main supply line to each of said equalizer means equalizing said plurality of bit line pairs in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of equalization potential sub-supply lines, respectively, and being operable to cut off the supply of said equalization potential sent from said equalization potential main supply line to said equalization potential sub-supply line corresponding to defective one among said memory array blocks.

Claim 21

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; a plurality of main word lines extending through said plurality of memory array blocks; a plurality of bit line pairs arranged in each of said plurality of memory array blocks along a direction crossing said main word lines and connected to said plurality of memory cells in the corresponding memory array blocks, wherein each of said plurality of memory array blocks includes a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines; said semiconductor memory device further comprises: a plurality of equalizer means provided correspondingly to said plurality of bit line pairs and each provided for equalizing potentials on the corresponding bit line pair; an equalization potential main supply line arranged along said plurality of memory array blocks and being provided for supplying an equalization potential for equalizing said plurality of bit line pairs; a plurality of equalization potential sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each being provided for transmitting said equalization potential supplied from said equalization potential main supply line to each of said equalizer means equalizing said plurality of bit line pairs in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of equalization potential sub-supply lines, respectively, and being operable to cut off the supply of said equalization potential sent from said equalization potential main supply line to said equalization potential sub-supply line corresponding to defective one among said memory array blocks.

Claim 22

The semiconductor memory device according to claim 17, wherein a column address is input after input of a row address, and said plurality of sub-word lines are activated selectively in all of said plurality of memory array blocks in relation to input of the row address.

Claim 23

The semiconductor memory device according to claim 17, wherein a row address and a column address are input simultaneously, and said plurality of sub-word lines are activated selectively in the selected memory array block among said plurality of memory array blocks in relation to input of the row address and the column address.

Claim 24

The semiconductor memory device according to claim 17, further comprising: a plurality of sense amplifier means provided correspondingly to said plurality of bit line pairs, respectively, each being operable to sense and amplify a potential difference on the corresponding bit line pair; and a plurality of switching means provided correspondingly to respective ones of said plurality of bit line pairs, between said memory cell array and said plurality of sense amplifier means, and each provided for switching the state of connection between said corresponding bit line pairs and said sense amplifier means, wherein said plurality of equalizer means are provided between said memory cell array and said plurality of switching means.

Claim 25

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; a plurality of main word lines extending through said plurality of memory array blocks; and a plurality of bit line pairs arranged in each of said plurality of memory array blocks along a direction crossing said main word lines and connected to said plurality of memory cells in the corresponding memory array blocks, wherein each of said plurality of memory array blocks includes a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines; and said semiconductor memory device further comprises: a plurality of sense amplifier means provided correspondingly to said plurality of bit line pairs and each being operable to sense and amplify a potential difference on the corresponding bit line pair; a sense amplifier activation signal main supply line arranged along said plurality of memory array blocks and being operable to supply a sense amplifier activation signal for activating said plurality of sense amplifier means; a plurality of sense amplifier activation signal sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each being operable to transmit said sense amplifier activation signal supplied from said sense amplifier activation signal main supply line to said plurality of sense amplifier means corresponding to said plurality of bit line pairs in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of sense amplifier activation signal sub-supply lines, respectively, and each being operable to cut off the supply of said sense amplifier activation signal from said sense amplifier activation signal main supply line to said sense amplifier activation signal sub-supply line corresponding to defective one among said memory array blocks.

Claim 26

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; a plurality of main word lines extending through said plurality of memory array blocks; and a plurality of bit line pairs arranged in each of said plurality of memory array blocks along a direction crossing said main word lines and connected to said plurality of memory cells in the corresponding memory array blocks, wherein each of said plurality of memory array blocks includes a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines; and said semiconductor memory device further comprises: a plurality of sense amplifier means provided correspondingly to said plurality of bit line pairs and each being operable to sense and amplify a potential difference on the corresponding bit line pair; a sense amplifier activation signal main supply line arranged along said plurality of memory array blocks and being operable to supply a sense amplifier activation signal for activating said plurality of sense amplifier means; a plurality of sense amplifier activation signal sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each being operable to transmit said sense amplifier activation signal supplied from said sense amplifier activation signal main supply line to said plurality of sense amplifier means corresponding to said plurality of bit line pairs in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of sense amplifier activation signal sub-supply lines, respectively, and each being operable to cut off the supply of said sense amplifier activation signal from said sense amplifier activation signal main supply line to said sense amplifier activation signal sub-supply line corresponding to defective one among said memory array blocks.

Claim 27

The semiconductor memory device according to claim 21, wherein a column address is input after input of a row address and said plurality of sub-word lines are activated selectively in all of said plurality of memory array blocks in relation to input of the row address.

Claim 28

The semiconductor memory device according to claim 21, wherein a row address and a column address are input simultaneously and said plurality of sub-word lines are activated selectively in the selected memory array block among said plurality of memory array blocks in relation to input of the row address and the column address.

Claim 29

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells and divided into a plurality of memory array blocks; a plurality of normal main word lines extending through said plurality of memory array blocks; a redundant main word line extending through said plurality of memory array blocks, wherein each of said memory array blocks includes: a plurality of normal sub-word lines connected to said plurality of main word lines, respectively, a plurality of normal memory cells connected to said plurality of normal sub-word lines, respectively, a redundant sub-word line connected to said redundant main word line, the defective normal sub-word line being replaceable with said redundant sub-word line, and a redundant memory cell connected to said redundant sub-word line; and said semiconductor memory device further comprises: a plurality of normal sub-word line activating means provided correspondingly to said plurality of memory array blocks, respectively, and each being operable to activate said plurality of normal sub-word lines in the corresponding memory array block; and a plurality of redundant sub-word line activating means provided correspondingly to said plurality of memory array blocks, respectively, and each being operable to activate said redundant sub-word line instead of defective one among said normal sub-word lines in the corresponding memory array block.

Claim 30

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells and divided into a plurality of memory array blocks; a plurality of normal main word lines extending through said plurality of memory array blocks; a redundant main word line extending through said plurality of memory array blocks, wherein each of said memory array blocks includes: a plurality of normal sub-word lines connected to said plurality of main word lines, respectively, a plurality of normal memory cells connected to said plurality of normal sub-word lines, respectively, a redundant sub-word line connected to said redundant main word line, the defective normal sub-word line being replaceable with said redundant sub-word line, and a redundant memory cell connected to said redundant sub-word line; and said semiconductor memory device further comprises: a plurality of normal sub-word line activating means provided correspondingly to said plurality of memory array blocks, respectively, and each being operable to activate said plurality of normal sub-word lines in the corresponding memory array block; and a plurality of redundant sub-word line activating means provided correspondingly to said plurality of memory array blocks, respectively, and each being operable to activate said redundant sub-word line instead of defective one among said normal sub-word lines in the corresponding memory array block.

Claim 31

The semiconductor memory device according to claim 24, further comprising: redundant main word line activating means for always activating said redundant main word line; each of said plurality of redundant sub-word line activating means receiving an address for selecting said normal sub-word line and activating the corresponding redundant sub-word line in response to the received address.

Claim 32

The semiconductor memory device according to claim 24, wherein a column address is input after input of a row address containing an address for selecting said normal sub-word line to be activated, and said plurality of normal sub-word line activating means and said plurality of redundant sub-word line activating means select the corresponding normal sub-word lines and the corresponding redundant sub-word lines related to said row address, respectively.

Claim 33

The semiconductor memory device according to claim 24, wherein a row address and a column address are input simultaneously, and said plurality of normal sub-word line activating means and said plurality of redundant sub-word line activating means select said plurality of corresponding normal sub-word lines and said redundant sub-word lines related to said row or column address, respectively.

Claim 34

The semiconductor memory device according to claim 24, wherein said memory cell array further includes a redundant memory array block; said redundant memory array block includes: a plurality of spare sub-word lines connected respectively to said plurality of normal main word lines, and a plurality of spare memory cells connected respectively to said plurality of spare sub-word lines; said semiconductor memory device further comprises spare sub-word line selecting means operable to activate said plurality of spare sub-word lines connected to said normal main word line connected to the defective normal sub-word line instead of said defective sub-word line in said memory array block; and said normal sub-word line in each of said memory array blocks can be replaced with said redundant sub-word line in the corresponding memory array block or said spare sub-word line connected to the corresponding normal main word line.

Claim 35

The semiconductor memory device according to claim 24, wherein each of said plurality of normal memory cells and said redundant memory cell includes a memory transistor and a memory capacitor; each of said plurality of memory array blocks includes a cell plate divided correspondingly to said plurality of memory array blocks and forming a common electrode of said memory capacitors of said plurality of normal memory cells and said redundant memory cell, respectively, in one memory array block; and said semiconductor memory device further comprises: a cell plate potential supply line for supplying a cell plate potential to said respective cell plates of said plurality of memory array blocks; and a plurality of cut-off means arranged between respective ones of said cell plates in said plurality of memory array blocks and said cell plate potential supply line, respectively, and being operable to cut off the supply of said cell plate potential to a defective one among said memory array blocks.

Claim 36

The semiconductor memory device according to claim 24, further comprising: a bit line pair arranged in each of said plurality of memory array blocks along a direction crossing said plurality of normal main word lines and said redundant main word line and connected to said plurality of normal memory cells, and said redundant memory cell in the corresponding memory array blocks; a plurality of equalizer means provided correspondingly to said plurality of bit line pairs corresponding to said plurality of memory array blocks, respectively, and each provided for equalizing potentials on the corresponding bit line pair; an equalization control signal main supply line arranged along said plurality of memory array blocks and provided for supplying an equalization control signal for controlling said plurality of equalizer means; a plurality of equalization control signal sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each provided for transmitting said equalization control signal supplied from said equalization control signal main supply line to said equalizer means equalizing said bit line pair in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of equalization control signal sub-supply lines, respectively, for cutting off the supply of said equalization control signal from said equalization control signal main supply line to said equalization control signal sub-supply line corresponding to defective one among said memory array blocks.

Claim 37

The semiconductor memory device according to claim 24, further comprising: a bit line pair arranged in each of said plurality of memory array blocks along the direction crossing said plurality of normal main word lines and said redundant main word line and connected to said plurality of normal memory cells and said redundant memory cell in the corresponding memory array blocks; a plurality of equalizer means provided correspondingly to respective ones of said plurality of bit line pairs corresponding to said plurality of memory array blocks, respectively, and each provided for equalizing the potential of the corresponding bit line pair; an equalization potential main supply line arranged along said plurality of memory array blocks for supplying an equalization potential equalizing said bit line pair in each memory array block, respectively; a plurality of equalization potential sub-supply line provided corresponding to said plurality of memory array blocks, respectively, and each provided for transmitting said equalization potential supplied from said equalization potential main supply line to said equalizer means equalizing said bit line pair in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of equalization potential sub-supply line, respectively, for cutting off the supply of said equalization potential from said equalization potential main supply line to said equalization potential sub-supply line corresponding to defective one among said memory array blocks.

Claim 38

The semiconductor memory device according to claim 24, further comprising: a bit line pair arranged in each of said plurality of memory array blocks along a direction crossing said plurality of normal main word lines and said redundant main word line and connected to said plurality of normal memory cells and said redundant memory cell in the corresponding memory array block; a plurality of sense amplifier means provided correspondingly to respective ones of said plurality of bit line pairs corresponding to said plurality of memory array blocks, respectively, and each being operable to sense and amplify a potential difference on the corresponding bit line pair; a plurality of switching means arranged between said corresponding bit line pairs and said sense amplifier means, respectively, for switching the state of connection between them; a switching control signal main supply line arranged along said plurality of memory array blocks for supplying a switching control signal for controlling said plurality of switching means; a plurality of switching control signal sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each being operable to transmit said switching control signal supplied from said switching control signal main supply line to the switching means corresponding to said bit line pair in the corresponding memory array block; and a plurality of cut off means provided correspondingly to said plurality of switching control signal sub-supply lines, respectively, and each being operable to cut off the supply of said switching control signal from said switching control signal main supply line to said switching control signal sub-supply line corresponding to defective one among said memory array blocks.

Claim 39

The semiconductor memory device according to claim 24, further comprising: a bit line pair arranged in each of said plurality of memory array blocks along a direction crossing said plurality of normal main word lines and said redundant main word line and connected to said plurality of normal memory cells and said redundant memory cell in the corresponding memory array block; a plurality of sense amplifier means provided correspondingly to respective ones of said plurality of bit line pairs corresponding to said plurality of memory array blocks, respectively, and each being operable to sense and amplify a potential difference on the corresponding bit line pair; a sense amplifier activation signal main supply line arranged along said plurality of memory array blocks and being operable to supply a sense amplifier activation signal for activating said plurality of sense amplifier means; a plurality of sense amplifier activation signal sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each being operable to transmit said sense amplifier activation signal supplied from said sense amplifier activation signal main supply line to said sense amplifier means corresponding to said bit line pair in the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of sense amplifier activation signal sub-supply lines, respectively, and each being operable to cut off the supply of said sense amplifier activation signal from said sense amplifier activation signal main supply line to said sense amplifier activation signal sub-supply line corresponding to defective one among said memory array blocks.

Claim 40

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells and divided into a plurality of normal memory array blocks and a redundant memory array block; a plurality of normal main word lines extending through said plurality of normal memory array blocks and said redundant memory array block, wherein each of said normal memory array blocks includes: a plurality of normal sub-word lines connected to said plurality of normal main word lines, respectively, a plurality of normal memory cells connected to said plurality of normal sub-word lines, respectively, and a normal bit line pair crossing said plurality of normal main word lines and receiving data selectively from said plurality of normal memory cells; said redundant memory array block includes: a plurality of redundant sub-word lines connected to said plurality of normal main word lines, respectively, a plurality of redundant memory cells connected to said plurality of redundant sub-word lines, and a redundant bit line pair crossing said plurality of normal main word lines and receiving data selectively from said plurality of redundant memory cells; each of said redundant sub-word lines can be replaced with defective one among said normal sub-word lines connected to the corresponding normal main word line; and said semiconductor memory device further comprises: a plurality of sense amplifier means provided correspondingly to said normal bit line pairs in said plurality of memory array blocks and said redundant bit line pair, respectively, and each being operable to sense and amplify a potential difference on the corresponding bit line pair; an input/output line pair transmitting the outputs sent from said plurality of sense amplifier means; a plurality of switching means arranged between said plurality of sense amplifier means and said input/output line pair, respectively, and being selectively turned on/off for selectively transmitting the outputs of said plurality of sense amplifier means to said input/output line pair; and an address comparison control means being operable to store precedingly an address corresponding to the normal sub-word line replaced with said redundant sub-word line, and compare said address with an address input for selecting said normal sub-word line, said address comparison control means controlling said plurality of switching means to transmit the output of said sense amplifier means corresponding to said redundant bit line pair to said input/output line pair when these addresses match each other, said address comparison control means controlling said plurality of switching means to transmit the output of said sense amplifier means corresponding to said normal bit line pair to said input/output line pair when these addresses do not match each other, and the amplifying operation by said plurality of sense amplifier means being performed in parallel with the address comparing operation by said address comparison control means.

Claim 41

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells and divided into a plurality of normal memory array blocks and a redundant memory array block; a plurality of normal main word lines extending through said plurality of normal memory array blocks and said redundant memory array block, wherein each of said normal memory array blocks includes: a plurality of normal sub-word lines connected to said plurality of normal main word lines, respectively, a plurality of normal memory cells connected to said plurality of normal sub-word lines, respectively, and a normal bit line pair crossing said plurality of normal main word lines and receiving data selectively from said plurality of normal memory cells; said redundant memory array block includes: a plurality of redundant sub-word lines connected to said plurality of normal main word lines, respectively, a plurality of redundant memory cells connected to said plurality of redundant sub-word lines, and a redundant bit line pair crossing said plurality of normal main word lines and receiving data selectively from said plurality of redundant memory cells; each of said redundant sub-word lines can be replaced with defective one among said normal sub-word lines connected to the corresponding normal main word line; and said semiconductor memory device further comprises: a plurality of sense amplifier means provided correspondingly to said normal bit line pairs in said plurality of memory array blocks and said redundant bit line pair, respectively, and each being operable to sense and amplify a potential difference on the corresponding bit line pair; an input/output line pair transmitting the outputs sent from said plurality of sense amplifier means; a plurality of switching means arranged between said plurality of sense amplifier means and said input/output line pair, respectively, and being selectively turned on/off for selectively transmitting the outputs of said plurality of sense amplifier means to said input/output line pair; and an address comparison control means being operable to store precedingly an address corresponding to the normal sub-word line replaced with said redundant sub-word line, and compare said address with an address input for selecting said normal sub-word line, said address comparison control means controlling said plurality of switching means to transmit the output of said sense amplifier means corresponding to said redundant bit line pair to said input/output line pair when these addresses match each other, said address comparison control means controlling said plurality of switching means to transmit the output of said sense amplifier means corresponding to said normal bit line pair to said input/output line pair when these addresses do not match each other, and the amplifying operation by said plurality of sense amplifier means being performed in parallel with the address comparing operation by said address comparison control means.

Claim 42

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells and divided into a plurality of normal memory array blocks and a redundant memory array block; and a plurality of normal main word lines extending through said plurality of normal memory array blocks and said redundant memory array block, wherein each of said normal memory array blocks includes: a plurality of normal sub-word lines connected to said plurality of normal main word lines, respectively, a plurality of normal memory cells connected to said plurality of normal sub-word lines, respectively, and a normal bit line pair crossing said plurality of normal main word lines and receiving data selectively from said plurality of normal memory cells; said redundant memory array block includes: a plurality of redundant sub-word lines connected to said plurality of normal main word lines, respectively, a plurality of redundant memory cells connected to said plurality of redundant sub-word lines, and a redundant bit line pair crossing said plurality of normal main word lines and receiving data selectively from said plurality of redundant memory cells; each of said redundant sub-word lines can be replaced with defective one among said normal sub-word lines connected to the corresponding normal main word line; said semiconductor memory device further comprises: a plurality of sense amplifier means provided correspondingly to said normal bit line pairs in said plurality of memory array blocks and said redundant bit line pair, respectively, and each being operable to sense and amplify a potential difference on the corresponding bit line pair; a plurality of input/output line pairs provided correspondingly to said plurality of sense amplifier means and each transmitting the output of the corresponding sense amplifier means; address comparing means for storing precedingly an address corresponding to said normal sub-word line replaced with said redundant sub-word line and comparing said address with an address input for selecting the normal sub-word line for outputting a result of the comparison; and multiplexer means for receiving information indicative of the result of comparison by said address comparing means, and being operable to output the potential difference on said input/output line pair transmitting the output of said sense amplifier means corresponding to said redundant bit line pair when the compared addresses match each other, and output the potential difference on said input/output line pair transmitting the output of said sense amplifier means corresponding to said normal bit line pair when the compared addresses do not match each other, the amplifying operation by said plurality of sense amplifier means being executed in parallel with the address comparing operation by said address comparing means.

Claim 43

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells and divided into a plurality of normal memory array blocks and a redundant memory array block; and a plurality of normal main word lines extending through said plurality of normal memory array blocks and said redundant memory array block, wherein each of said normal memory array blocks includes: a plurality of normal sub-word lines connected to said plurality of normal main word lines, respectively, a plurality of normal memory cells connected to said plurality of normal sub-word lines, respectively, and a normal bit line pair crossing said plurality of normal main word lines and receiving data selectively from said plurality of normal memory cells; said redundant memory array block includes: a plurality of redundant sub-word lines connected to said plurality of normal main word lines, respectively, a plurality of redundant memory cells connected to said plurality of redundant sub-word lines, and a redundant bit line pair crossing said plurality of normal main word lines and receiving data selectively from said plurality of redundant memory cells; each of said redundant sub-word lines can be replaced with defective one among said normal sub-word lines connected to the corresponding normal main word line; said semiconductor memory device further comprises: a plurality of sense amplifier means provided correspondingly to said normal bit line pairs in said plurality of memory array blocks and said redundant bit line pair, respectively, and each being operable to sense and amplify a potential difference on the corresponding bit line pair; a plurality of input/output line pairs provided correspondingly to said plurality of sense amplifier means and each transmitting the output of the corresponding sense amplifier means; address comparing means for storing precedingly an address corresponding to said normal sub-word line replaced with said redundant sub-word line and comparing said address with an address input for selecting the normal sub-word line for outputting a result of the comparison; and multiplexer means for receiving information indicative of the result of comparison by said address comparing means, and being operable to output the potential difference on said input/output line pair transmitting the output of said sense amplifier means corresponding to said redundant bit line pair when the compared addresses match each other, and output the potential difference on said input/output line pair transmitting the output of said sense amplifier means corresponding to said normal bit line pair when the compared addresses do not match each other, the amplifying operation by said plurality of sense amplifier means being executed in parallel with the address comparing operation by said address comparing means.

Claim 44

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells; and a plurality of main word lines extending through said memory cell array, wherein said memory cell array is divided into: a plurality of normal memory array blocks and, a redundant memory array block for replacing a defective one among said normal memory array blocks; each of said normal and redundant memory array blocks has a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines, respectively; and said sub-word lines connected to said main word lines to be activated are activated in all of said plurality of normal memory array blocks and said redundant memory array block in a refresh operation.

Claim 45

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cells; and a plurality of main word lines extending through said memory cell array, wherein said memory cell array is divided into: a plurality of normal memory array blocks and, a redundant memory array block for replacing a defective one among said normal memory array blocks; each of said normal and redundant memory array blocks has a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines, respectively; and said sub-word lines connected to said main word lines to be activated are activated in all of said plurality of normal memory array blocks and said redundant memory array block in a refresh operation.

Claim 46

A semiconductor memory device wherein row and column addresses are successively input, and a memory cell is selected in accordance with said input row and column addresses, comprising: a memory cell array having a plurality of dynamic memory cells; and a plurality of main word lines extending through said memory cell array and selected in accordance with said row address, wherein said memory cell array is divided into: a plurality of normal memory array blocks, and a redundant memory array block for replacing a defective one among said normal memory array blocks; each of said normal and redundant memory array blocks has a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines, respectively; and said sub-word lines connected to said main word lines to be activated are activated in all of said plurality of normal memory array blocks and said redundant memory array block in a normal operation and a refresh operation.

Claim 47

A semiconductor memory device wherein row and column addresses are successively input, and a memory cell is selected in accordance with said input row and column addresses, comprising: a memory cell array having a plurality of dynamic memory cells; and a plurality of main word lines extending through said memory cell array and selected in accordance with said row address, wherein said memory cell array is divided into: a plurality of normal memory array blocks, and a redundant memory array block for replacing a defective one among said normal memory array blocks; each of said normal and redundant memory array blocks has a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines, respectively; and said sub-word lines connected to said main word lines to be activated are activated in all of said plurality of normal memory array blocks and said redundant memory array block in a normal operation and a refresh operation.

Claim 48

A semiconductor memory device wherein a memory cell is selected in accordance with simultaneously input row and column addresses, comprising: a memory cell array having a plurality of dynamic memory cells; and a plurality of main word lines extending through said memory cell array and are selected in accordance with said row address, wherein said memory cell array is divided into: a plurality of normal memory array blocks, and a redundant memory array block for replacing a defective one among said normal memory array blocks; each of said plurality of normal memory array blocks and said redundant memory array block has a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines, respectively; and said sub-word lines connected to said main word lines to be activated are activated in all of said plurality of normal memory array blocks and said redundant memory array block in a refresh operation.

Claim 49

A semiconductor memory device wherein a memory cell is selected in accordance with simultaneously input row and column addresses, comprising: a memory cell array having a plurality of dynamic memory cells; and a plurality of main word lines extending through said memory cell array and are selected in accordance with said row address, wherein said memory cell array is divided into: a plurality of normal memory array blocks, and a redundant memory array block for replacing a defective one among said normal memory array blocks; each of said plurality of normal memory array blocks and said redundant memory array block has a plurality of sub-word lines connected to said plurality of memory cells in said memory array block and connected to said plurality of main word lines, respectively; and said sub-word lines connected to said main word lines to be activated are activated in all of said plurality of normal memory array blocks and said redundant memory array block in a refresh operation.

Claim 50

A semiconductor memory device, comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; and a plurality of main word lines extending through said plurality of memory array blocks, wherein each of said plurality of memory array blocks includes a plurality of sub-word lines connected to said plurality of memory cells in the memory array block and connected to said plurality of main word lines, respectively; and said semiconductor memory device further comprises: a main supply line arranged along said plurality of memory array blocks for supplying a potential employed for the operation of said plurality of memory array blocks; a plurality of sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each provided for further transmission of said potential supplied from said main supply line for the operation of the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of sub-supply line, respectively, and being operable to cut off the supply of said potential from said main supply line to said sub-supply line corresponding to defective one among said memory array blocks.

Claim 51

A semiconductor memory device, comprising: a memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks; and a plurality of main word lines extending through said plurality of memory array blocks, wherein each of said plurality of memory array blocks includes a plurality of sub-word lines connected to said plurality of memory cells in the memory array block and connected to said plurality of main word lines, respectively; and said semiconductor memory device further comprises: a main supply line arranged along said plurality of memory array blocks for supplying a potential employed for the operation of said plurality of memory array blocks; a plurality of sub-supply lines provided correspondingly to said plurality of memory array blocks, respectively, and each provided for further transmission of said potential supplied from said main supply line for the operation of the corresponding memory array block; and a plurality of cut-off means provided correspondingly to said plurality of sub-supply line, respectively, and being operable to cut off the supply of said potential from said main supply line to said sub-supply line corresponding to defective one among said memory array blocks.

Claim 52

The semiconductor memory device according to claim 39, wherein said potential supplied from said main supply line and said sub-supply line is a signal potential.

Claim 53

The semiconductor memory device according to claim 39, wherein said potential supplied from said main supply line and said sub-supply line is a potential for defining the potential in said memory array block.