US5795819A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated pad and fuse structure for planar copper metallurgy
Assignee: GlobalFoundries Inc
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Filing: 1997-09-09
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Granted: 1998-08-18
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Expires: 2017-09-09
Abstract
Abstract A semiconductor interconnection consists of a corrosion resistant integrated fuse and Controlled, Collapse Chip Connection (C4) structure for the planar copper Back End of Line (BEOL). Non copper fuse material is directly connected to copper wiring.
Inventors
- 👤 William Thomas Motsiff
- 👤 Robert Michael Geffken
- 👤 Ronald Robert Uttecht
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:01
CPC Classifications
H; H01; H01H; H01H85/00; H01H85/02; H01H85/04; H01H85/041; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10W20/494
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
80 words
A method of making an interconnection structure for a semiconductor circuit comprising the steps of: providing a substrate having coplanar damascene non-self-passivating conductors embedded in a first insulator defining a first electrical interconnect layer; forming second electrical interconnect layer comprising coplanar self-passivating conductors in a second insulator, said second electrical interconnect layer overlying said first electrical interconnect layer and said second interconnect self-passivating conductors contacting said non-self-passivating conductors; and depositing a final passivation layer over said second electrical interconnect layer.
Claim 2
Independent Claim
80 words
A method of making an interconnection structure for a semiconductor circuit comprising the steps of: providing a substrate having coplanar damascene non-self-passivating conductors embedded in a first insulator defining a first electrical interconnect layer; forming second electrical interconnect layer comprising coplanar self-passivating conductors in a second insulator, said second electrical interconnect layer overlying said first electrical interconnect layer and said second interconnect self-passivating conductors contacting said non-self-passivating conductors; and depositing a final passivation layer over said second electrical interconnect layer.
Claim 3
Dependent Claim
59 words
The method of making an interconnection structure of claim 1, wherein one of said self-passivating conductors (in contact with one of said non-self-passivating conductors) forms part of a Controlled, Collapse Chip Connection (C4) barrier structure, the method further comprising the steps of: etching the final passivation layer above the C4 barrier structure; and depositing pad limiting and C4 metallurgies.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-17 | 2002-02-16 | 2002-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-17 | 2006-02-16 | 2006-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-17 | 2010-02-16 | 2010-08-18 | $7700.00 | Window Closed / Lapsed |