Digital delay circuit and method

Claim 2

A digital delay circuit comprising: a digital calibration circuit having a sample gate output line; wherein in an auto-calibration operation mode of said digital delay circuit, said digital calibration circuit generates a sample gate signal having a second state on said sample gate output line; and a digital delayed signal generator having: a signal input line; a delayed signal output line; a feedback input terminal; a feedback line connected to said digital calibration circuit and to said feedback input terminal of said digital delayed signal generator; a digital signal delay chain having an input terminal and a plurality of signal delay taps; an input signal select terminal connected to said sample gate output line wherein in response to said sample gate signal having a first state on said sample gate output line, said signal input line is connected to said input terminal of said digital signal delay chain for a normal mode of operation; and in response to said sample gate signal having said second state, said feedback input terminal is connected to said input terminal of said digital signal delay chain, and a delay tap in said plurality of signal delay taps having a specified time delay is connected to said feedback line so that said digital signal delay chain is used in both said auto-calibration mode of operation and in said normal mode of operation.

Claim 3

A digital delay circuit as in claim 1 wherein said digital calibration circuit further comprises a calibration control input line wherein said digital calibration circuit generates said sample gate signal having said second state in response to an active signal on said calibration control input line.

Claim 4

A digital delay circuit as in claim 2 wherein said a digital calibration circuit further comprises: a calibration control logic circuit connected to said calibration control input line and to said sample gate output line wherein said calibration control logic circuit generates said sample gate signal having said second state on said sample gate output line in response to said active signal on said calibration control input line.

Claim 5

A digital delay circuit as in claim 3 wherein said digital calibration circuit further comprises: a calibration counter circuit connected to said sample gate output line and to said feedback line, and having a counter output bus wherein in response to said sample gate signal having said second state, said calibration counter circuit counts a signal on said feedback line.

Claim 6

A digital delay circuit as in claim 4 wherein said digital calibration circuit further comprises: a count decoder circuit connected to said counter output bus, and having a delay time select bus wherein in response to a signal on said counter output bus, said count decoder circuit generates a signal on said delay time select bus to select a time delay.

Claim 7

A digital delay circuit as in claim 5 wherein said digital delayed signal generator further comprises an output signal selector connected to said plurality of signal delay taps, said feedback line, said delay time select bus, said delayed signal output line, and said sample gate output line wherein in response to said sample gate signal having said first state on said sample gate output line and said signal on said delay time select bus, said output signal selector passes one signal from said plurality of signal delay taps to said delayed signal output line; and in response to said sample gate signal having said second state, said output signal selector connects said delay tap in said plurality of signal delay taps having said specified time delay to said feedback line.

Claim 8

A digital delay circuit as in claim 1 wherein said digital calibration circuit further comprises a delay time select bus wherein upon said sample gate signal going from said second state to said first state, said digital calibration circuit generates a signal on said delay time select bus to select a time delay for an input signal on said signal input line.

Claim 9

A digital delay circuit as in claim 7 wherein said digital delayed signal generator further comprises an output signal selector connected to said plurality of signal delay taps, said feedback line, said delay time select bus, said delayed signal output line, and said sample gate output line wherein in response to a sample gate signal having said first state on said sample gate output line and a signal on said delay time select bus, said output signal selector passes one signal from said plurality of signal delay taps to said delayed signal output line; and in response to said sample gate signal having said second state, said output signal selector connects said delay tap in said plurality of signal delay taps having said specified time delay to said feedback line.

Claim 10

A digital delay circuit as in claim 1 wherein said digital signal delay chain comprises a ring oscillator.

Claim 11

A digital delay circuit as in claim 1 wherein said digital signal delay chain comprises a plurality of logic gates.

Claim 12

The digital delay circuit as in claim 1 wherein delayed signal output line is coupled to a filter.

Claim 13

The digital delay circuit as in claim 11 wherein said filter is a deglitching filter.

Claim 14

The digital delay circuit as in claim 1 wherein delayed signal output line is coupled to a data separator.

Claim 15

A digital delay circuit comprising: a digital calibration circuit having: a calibration control input line; a feedback input terminal; a sample gate output line; and a delay time select bus wherein in response to an active signal on said calibration control input line, said digital calibration circuit generates a sample gate signal having a second state on said sample gate output line to place said digital delay circuit in an auto-calibration mode; and a digital delayed signal generator connected to said delay time select bus and to said sample gate output line, and having: a signal input line; a delayed signal output line; a feedback input terminal; a feedback line connected to said feedback input terminal of said digital calibration circuit and to said feedback input terminal of said digital delayed signal generator; and a digital signal delay chain having an input terminal coupled to said signal input line and to said feedback input terminal, and a plurality of signal delay taps; wherein in response to a signal on said delay time select bus and a first state of said sample gate signal, said digital delayed signal generator connects one of said plurality of signal delay taps to said delayed signal output line for a normal delay mode of operation; and in response to said sample gate signal having said second state, said feedback input terminal of said digital delayed signal generator is connected to said input terminal of said digital signal delay chain, and a delay tap in said plurality of signal delay taps having a specified time delay is connected to said feedback line.

Claim 16

A digital delay circuit comprising: a digital calibration circuit having: a calibration control input line; a feedback input terminal; a sample gate output line; and a delay time select bus wherein in response to an active signal on said calibration control input line, said digital calibration circuit generates a sample gate signal having a second state on said sample gate output line to place said digital delay circuit in an auto-calibration mode; and a digital delayed signal generator connected to said delay time select bus and to said sample gate output line, and having: a signal input line; a delayed signal output line; a feedback input terminal; a feedback line connected to said feedback input terminal of said digital calibration circuit and to said feedback input terminal of said digital delayed signal generator; and a digital signal delay chain having an input terminal coupled to said signal input line and to said feedback input terminal, and a plurality of signal delay taps; wherein in response to a signal on said delay time select bus and a first state of said sample gate signal, said digital delayed signal generator connects one of said plurality of signal delay taps to said delayed signal output line for a normal delay mode of operation; and in response to said sample gate signal having said second state, said feedback input terminal of said digital delayed signal generator is connected to said input terminal of said digital signal delay chain, and a delay tap in said plurality of signal delay taps having a specified time delay is connected to said feedback line.

Claim 17

A digital delay circuit as in claim 14 wherein said a digital calibration circuit further comprises: a calibration control logic circuit connected to said calibration control input line and to said sample gate output line wherein said calibration control logic circuit generates said sample gate signal having said second state on said sample gate output line in response to said active signal on said calibration control input line.

Claim 18

A digital delay circuit as in claim 15 wherein said a digital calibration circuit further comprises: a calibration counter circuit connected to said sample gate output line and to said feedback input terminal, and having a counter output bus wherein in response to said sample gate signal having said second state, said calibration counter circuit counts oscillations of a signal on said feedback input terminal.

Claim 19

A digital delay circuit as in claim 16 wherein said digital calibration circuit further comprises: a count decoder circuit connected to said counter output bus, and to said delay time select bus wherein in response to a signal on said counter output bus, said count decoder circuit generates a said signal on said delay time select bus to select a time delay for a signal on said signal input line.

Claim 20

The digital delay circuit as in claim 14 wherein said signal on said delayed signal output line of said digital delay circuit is coupled to a filter.

Claim 21

The digital delay circuit as in claim 18 wherein said filter is a deglitching filter.

Claim 22

The digital delay circuit as in claim 14 wherein said delayed signal output line of said digital delay circuit is coupled to a data separator.

Claim 25

The method of claim 21 wherein calibrating a time delay further comprises: generating a sample gate signal having a second state in response to an active signal on a calibration control input line of a digital calibration circuit wherein said sample gate signal is generated on a sample gate output line of said digital calibration circuit and said input terminal of said digital delay chain is connected to said delay tap in said plurality of signal delay taps having said specified time delay in response to said sample gate signal having said second state.

Claim 26

The method of claim 22 wherein generating said sample gate signal having said second state on said sample gate output line in response to said active signal on said calibration control input line further comprises: generating said sample gate signal by a calibration control logic circuit connected to said calibration control input line and to said sample gate output line.

Claim 27

The method of claim 21 wherein calibrating a time delay further comprises: counting a signal from said delay tap in said plurality of signal delay taps having said specified time delay to obtain a count.

Claim 28

The method of claim 24 wherein calibrating a time delay further comprises: decoding said count to obtain a signal representing said calibrated time delay.

Claim 29

The method of claim 25 wherein calibrating a time delay further comprises: applying said signal representing said calibrated time delay to an output signal selector connected to said plurality of signal delay taps wherein said output signal selector passes one signal from said plurality of signal delay taps to said delayed signal output line and said one signal is said delayed output signal.