US5789802A
Expired / Lapsed
US
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Dopant profile spreading for arsenic source/drain
Assignee: TDK Micronas GmbH
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Filing: 1996-06-21
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Granted: 1998-08-04
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Expires: 2016-06-21
Abstract
Abstract An improved process for forming shallow arsenic-doped source/drain regions in MOS devices utilizes a two-step arsenic implant which lowers the surface arsenic concentration while maintaining sharp junction profile and desired junction depth. Minimizing the excess arsenic in the surface region improves silicidation characteristics.
Inventors
- 👤 Nicholas H. Tripsas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:43
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/80; H10D62/83; H10D62/834; H10D64/00; H10D64/60; H10D64/62; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/013; H10D84/02; H10D84/03; H10D84/038; H10P30/21; H10P30/212; H10P30/28; B; B26; B26F; B26F1/00; B26F1/38; B26F1/384
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
307 words
An NMOS device in a surface of a silicon substrate, said device having a source/drain region therein comprising; an arsenic-doped region extending into said silicon substrate from said surface, said arsenic-doped region having a leading edge below said surface; a junction between said leading edge of said arsenic doped region and said substrate at a specified junction depth below said surface; said device being made by a process comprising (1) implanting a first dose of arsenic into said silicon substrate with a first energy; (2) implanting a second dose of arsenic into said silicon substrate with a second energy; (3) annealing said silicon substrate at an anneal temperature; (4) adjusting said first and second doses of arsenic and said first and second energies to provide a first profile of chemical arsenic concentration and a second profile of electrically active arsenic concentration in said arsenic-doped region following said annealing step and to provide said junction at said specified junction depth; said first profile of chemical arsenic concentration being a non-Gaussian profile as a function of depth below said surface and said second profile of electrically active arsenic concentration being a non-Gaussian profile as a function of depth below said surface said chemical concentration at said surface being greater than and substantially within a factor of two of said electrically active arsenic concentration at said surface, said chemical concentration profile having a knee at a knee depth below said surface, and said chemical concentration profile being substantially flatter than a Gaussian profile for depths less than said knee depth, said chemical concentration being greater than said electrically active arsenic concentration for depths less than said knee depth, said electrically active arsenic concentration profile for depths less than said knee depth being substantially flat and substantially equal to the solid solubility limit of arsenic in silicon at said anneal temperature.
Claim 2
Dependent Claim
307 words
An NMOS device in a surface of a silicon substrate, said device having a source/drain region therein comprising; an arsenic-doped region extending into said silicon substrate from said surface, said arsenic-doped region having a leading edge below said surface; a junction between said leading edge of said arsenic doped region and said substrate at a specified junction depth below said surface; said device being made by a process comprising (1) implanting a first dose of arsenic into said silicon substrate with a first energy; (2) implanting a second dose of arsenic into said silicon substrate with a second energy; (3) annealing said silicon substrate at an anneal temperature; (4) adjusting said first and second doses of arsenic and said first and second energies to provide a first profile of chemical arsenic concentration and a second profile of electrically active arsenic concentration in said arsenic-doped region following said annealing step and to provide said junction at said specified junction depth; said first profile of chemical arsenic concentration being a non-Gaussian profile as a function of depth below said surface and said second profile of electrically active arsenic concentration being a non-Gaussian profile as a function of depth below said surface said chemical concentration at said surface being greater than and substantially within a factor of two of said electrically active arsenic concentration at said surface, said chemical concentration profile having a knee at a knee depth below said surface, and said chemical concentration profile being substantially flatter than a Gaussian profile for depths less than said knee depth, said chemical concentration being greater than said electrically active arsenic concentration for depths less than said knee depth, said electrically active arsenic concentration profile for depths less than said knee depth being substantially flat and substantially equal to the solid solubility limit of arsenic in silicon at said anneal temperature.
Claim 3
Dependent Claim
90 words
The NMOS device of claim 1, wherein: said chemical arsenic concentration at said surface is in the range between 1e19-1e21; said junction depth is in the range between 0.05-0.2 microns, and wherein the sheet resistance of said arsenic-doped region is in the range between 50-500 ohms per square; said second arsenic energy is greater than said first arsenic energy; said first arsenic dose and first arsenic energy are sufficiently high to form a disordered layer near said surface of said silicon wafer for inhibiting channeling during said second implantation step.
Claim 4
Dependent Claim
28 words
The NMOS device of claim 2, further comprising a layer of titanium silicide at the surface of said arsenic-doped region to form a contact to said arsenic-doped region.
Claim 5
Dependent Claim
219 words
The device of claim 13, wherein said process for making said device further comprises: (1) providing said silicon substrate having a thin oxide layer thereon; (2) annealing said substrate after said first and second implant at a first anneal temperature for a first time, wherein said first and second implant doses and said first and second implant energies are adjusted so as to provide a chemical concentration of said arsenic at said surface substantially equal to the solid solubility of arsenic in silicon at said first anneal temperature; (3) removing said oxide layer; (4) depositing a layer of titanium over said surface region; (5) annealing said substrate at a second anneal temperature for a second anneal time, said second temperature and time being sufficiently high to react substantially all of said titanium with said silicon to form said titanium silicide layer over said surface region; wherein said first anneal temperature is in the range between 800-1100 C, said second anneal temperature is in the range between 600 and 800C, said surface chemical arsenic concentration is in the range between 1e19-1e21, said first energy is in the range between 1e14-2e15, said first dose is in the range between 2-40 KeV, said second energy is in the range between 10-90 KeV, and said second dose is in the range between 5e14-5e15.
Claim 6
Dependent Claim
195 words
The device of claim 3, wherein: the thickness of said titanium silicide layer is in the range between 200-1000 Angstroms, and wherein the sheet resistance of said titanium silicide layer is less than 20 ohms per square; and wherein said process for making said device further comprises: (1) providing said silicon substrate having a thin oxide layer thereon; (2) annealing said substrate at a first anneal temperature for a first time, wherein said first and second implant doses and said first and second implant energies are adjusted so as to provide a chemical concentration of said arsenic at said surface substantially equal to the solid solubility of arsenic in silicon at said first anneal temperature; (3) removing said oxide layer; (4) depositing a layer of titanium over said surface region; (5) annealing said substrate at a second anneal temperature for a second anneal time, said second temperature and time being sufficiently high to react substantially all of said titanium with said silicon to form said titanium silicide layer over said surface region; wherein said first anneal temperature is in the range between 800-1100C, and said surface chemical arsenic concentration is in the range between 1e19-1e21.
Claim 7
Dependent Claim
228 words
An NMOS device in a surface of a silicon substrate, said device having a source/drain region therein comprising: an arsenic-doped region extending into said silicon substrate from said surface, said arsenic-doped region having a leading edge below said surface, said arsenic-doped region having been formed by ion implantation of arsenic atoms followed by post-implant anneal at an anneal temperature; a junction between said leading edge of said arsenic doped region and said substrate at a specified junction depth below said surface; said arsenic-doped region having a first non-Gaussian profile of chemical arsenic concentration as a function of depth below said surface and having a second non-Gaussian profile of electrically active arsenic concentration as a function of depth below said surface, said chemical concentration at said surface being greater than and substantially within a factor of two of said electrically active arsenic concentration at said surface, said chemical concentration profile having a knee at a knee depth below said surface, and said chemical concentration profile being substantially flatter than a Gaussian profile for depths less than said knee depth, said chemical concentration being greater than said electrically active arsenic concentration for depths less than said knee depth, said electrically active arsenic concentration profile for depths less than said knee depth being substantially flat and substantially equal to the solid solubility limit of arsenic in silicon at said anneal temperature.
Claim 8
Dependent Claim
228 words
An NMOS device in a surface of a silicon substrate, said device having a source/drain region therein comprising: an arsenic-doped region extending into said silicon substrate from said surface, said arsenic-doped region having a leading edge below said surface, said arsenic-doped region having been formed by ion implantation of arsenic atoms followed by post-implant anneal at an anneal temperature; a junction between said leading edge of said arsenic doped region and said substrate at a specified junction depth below said surface; said arsenic-doped region having a first non-Gaussian profile of chemical arsenic concentration as a function of depth below said surface and having a second non-Gaussian profile of electrically active arsenic concentration as a function of depth below said surface, said chemical concentration at said surface being greater than and substantially within a factor of two of said electrically active arsenic concentration at said surface, said chemical concentration profile having a knee at a knee depth below said surface, and said chemical concentration profile being substantially flatter than a Gaussian profile for depths less than said knee depth, said chemical concentration being greater than said electrically active arsenic concentration for depths less than said knee depth, said electrically active arsenic concentration profile for depths less than said knee depth being substantially flat and substantially equal to the solid solubility limit of arsenic in silicon at said anneal temperature.
Claim 9
Dependent Claim
16 words
The device of claim 12, wherein said junction depth is in the range between 0.08-0.2 microns.
Claim 10
Dependent Claim
27 words
The device of claim 12, further comprising a layer of titanium silicide at the surface of said arsenic-doped region to form a contact to said arsenic-doped region.
Claim 11
Dependent Claim
37 words
The device of claim 8, wherein the thickness of said titanium silicide layer is in the range between 200-1000 Angstroms, and wherein the sheet resistance of said titanium silicide layer is less than 20 ohms per square.
Claim 12
Dependent Claim
16 words
The device of claim 9, wherein said junction depth is in the range between 0.08-0.2 microns.
Claim 13
Dependent Claim
19 words
The device of claim 6, wherein said chemical arsenic concentration at said surface is in the range between 1e19-1e21.
Claim 14
Dependent Claim
34 words
The device of claim 11, where said junction depth is in the range between 0.05-0.2 microns, and wherein the sheet resistance of said arsenic-doped region is in the range between 50-500 ohms per square.
Claim 15
Dependent Claim
27 words
The device of claim 6, further comprising a layer of titanium silicide at the surface of said arsenic-doped region to form a contact to said arsenic-doped region.
Claim 16
Dependent Claim
37 words
The device of claim 13, wherein the thickness of said titanium silicide layer is in the range between 200-1000 Å, and wherein the sheet resistance of said titanium silicide layer is less than 20 ohms per square.
References Cited (Backward Citations)
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