Compound semiconductor device

Claim 2

A compound semiconductor device comprising: a first compound semiconductor layer; a second compound semiconductor layer, containing at least one of In and Al, which is in contact with the first compound semiconductor layer to generate a two dimensional electron gas layer in an interface between the first and second compound semiconductor layers; a third compound semiconductor layer comprising doped GaAs and coated on the second compound semiconductor layer, wherein said second and third compound semiconductor layers form an electron supplying layer; a source electrode and a drain electrode electrically connected to the two dimensional electron gas layer; a gate electrode formed between the source electrode and the drain electrode so as to be in Schottky contact with the third compound semiconductor layer; and an insulating film formed in contact with the third compound semiconductor layer and between the gate electrode and the source electrode, and formed in contact with the third compound semiconductor layer and between the gate electrode and the drain electrode.

Claim 3

The device as set forth in claim 1, wherein the source electrode and the drain electrode are electrically connected to the two dimensional electron gas layer through the second compound semiconductor layer and the third compound semiconductor layer.

Claim 4

The device as set forth in claim 2, further comprising: a fourth compound semiconductor layer formed between the source electrode and the third compound semiconductor layer and between the drain electrode and the third compound semiconductor layer; and the gate electrode extending from the third compound semiconductor layer up to above the fourth compound semiconductor layer to form an extended part above the fourth compound semiconductor layer, and the insulating film being formed between the extended part of the gate electrode and the fourth compound semiconductor layer.

Claim 5

The device as set forth in claim 1, wherein the insulating film consists of one of SiO 2 , SiN and SiON.

Claim 6

The device as set forth in claim 1, wherein the second compound semiconductor layer consists of one of InP, InGaP, InGaAsP, InAlAs and InSb.

Claim 7

The device as set forth in claim 3, wherein the fourth compound semiconductor layer comprises: a surface layer consisting of a GaAs layer; and a compound semiconductor layer, having an etching rate different from that of the surface layer, formed between the surface layer and the third compound semiconductor layer.

Claim 8

The device as set forth in claim 6, wherein the compound semiconductor layer having a different etching rate consists of one of InGaP, AlGaAs and AlInAs.

Claim 9

The device as set forth in claim 1, wherein the third compound semiconductor layer has a thickness of 1 Å to 500 Å.

Claim 10

A compound semiconductor device, comprising: a first compound semiconductor layer having a first surface; a second compound semiconductor layer containing one of In and Al, having a first surface and a second surface, said first surface of said second compound semiconductor layer formed on said first surface of said first compound semiconductor layer to generate a two dimensional electron gas layer between the first and second compound semiconductor layers; a third compound semiconductor layer comprising doped GaAs and having a first surface and a second surface, said first surface of said third compound semiconductor layer formed on said second surface of said second compound semiconductor layer; a fourth compound semiconductor layer having a first surface and a second surface, said first surface of said fourth compound semiconductor layer formed on said second surface of said third compound semiconductor layer, an opening having walls being formed in said fourth compound semiconductor layer to create a first region and a second region of said fourth compound semiconductor layer, top surfaces of said first and second regions forming said second surface of said fourth compound semiconductor; a source electrode and a drain electrode electrically connected to said two dimensional electron gas layer and respectively formed on said top surfaces of said first and second regions; a gate electrode extending in the opening from the second surface of the third compound semiconductor layer to above a height of said source and drain electrodes; and an insulating film being in contact with and extending from said second surface of said third compound semiconductor layer, along the walls of the opening to portions of said top surfaces of said first and second regions, said insulating film being between said gate electrode and each of said source and drain electrodes and between said gate electrode and said fourth compound semiconductor layer.

Claim 11

A compound semiconductor device, comprising: a first compound semiconductor layer having a first surface; a second compound semiconductor layer containing one of In and Al, having a first surface and a second surface, said first surface of said second compound semiconductor layer formed on said first surface of said first compound semiconductor layer to generate a two dimensional electron gas layer between the first and second compound semiconductor layers; a third compound semiconductor layer comprising doped GaAs and having a first surface and a second surface, said first surface of said third compound semiconductor layer formed on said second surface of said second compound semiconductor layer; a fourth compound semiconductor layer having a first surface and a second surface, said first surface of said fourth compound semiconductor layer formed on said second surface of said third compound semiconductor layer, an opening having walls being formed in said fourth compound semiconductor layer to create a first region and a second region of said fourth compound semiconductor layer, top surfaces of said first and second regions forming said second surface of said fourth compound semiconductor; a source electrode and a drain electrode electrically connected to said two dimensional electron gas layer and respectively formed on said top surfaces of said first and second regions; a gate electrode extending in the opening from the second surface of the third compound semiconductor layer to above a height of said source and drain electrodes; and an insulating film being in contact with and extending from said second surface of said third compound semiconductor layer, along the walls of the opening to portions of said top surfaces of said first and second regions, said insulating film being between said gate electrode and each of said source and drain electrodes and between said gate electrode and said fourth compound semiconductor layer.

Claim 12

The compound semiconductor device as claimed in claim 9, wherein said insulating film consists of one of SiO 2 , SiN and SiON.

Claim 13

The compound semiconductor device as claimed in claim 9, wherein said fourth compound semiconductor layer comprises: a surface layer consisting of GaAs; and a compound semiconductor layer having an etching rate different from that of said surface layer and formed between said surface layer and said third compound semiconductor layer.