US5787488A
Expired / Lapsed
US
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Multi-phase multi-access pipeline memory system
Assignee: Analog Devices Inc
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Filing: 1997-01-06
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Granted: 1998-07-28
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Expires: 2017-01-06
Abstract
Abstract A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for application to each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.
Inventors
- 👤 Douglas Garde
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:49
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1615
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
170 words
A dual phase, dual access pipeline memory system comprising: first and second processors; a pipeline memory including latch means; bus means for interconnecting said processors and pipeline memory; a clock circuit responsive to a system clock signal for providing a first clock signal in phase with said system clock signal for accessing said first processor, a second clock signal out of phase with said system clock signal for accessing said second processor out of phase with said first processor, and a third clock signal at twice the system clock signal rate for clocking said pipeline memory through said latch means to allow an address to be supplied to said pipeline memory by said first processor during one phase while said first processor is accessing data from the previous cycle in the same phase and, conversely, to allow an address to be supplied to said pipeline memory by said second processor during the other phase while the said second processor is accessing data from the previous cycle in the same phase.
Claim 2
Dependent Claim
170 words
A dual phase, dual access pipeline memory system comprising: first and second processors; a pipeline memory including latch means; bus means for interconnecting said processors and pipeline memory; a clock circuit responsive to a system clock signal for providing a first clock signal in phase with said system clock signal for accessing said first processor, a second clock signal out of phase with said system clock signal for accessing said second processor out of phase with said first processor, and a third clock signal at twice the system clock signal rate for clocking said pipeline memory through said latch means to allow an address to be supplied to said pipeline memory by said first processor during one phase while said first processor is accessing data from the previous cycle in the same phase and, conversely, to allow an address to be supplied to said pipeline memory by said second processor during the other phase while the said second processor is accessing data from the previous cycle in the same phase.
Claim 3
Dependent Claim
22 words
The dual phase, dual access pipeline memory system of claim 1 in which said processors are an I/O processor and a microprocessor.
Claim 4
Dependent Claim
18 words
The dual phase, dual access pipeline memory system of claim 1 in which said processors are both microprocessors.
Claim 5
Dependent Claim
21 words
The dual, phase dual access pipeline memory system of claim 1 in which said processors include subprocessors in the same microprocessor.
Claim 6
Dependent Claim
25 words
The dual phase, dual access pipeline memory system of claim 4 in which said subprocessors include an instruction fetch unit and a data fetch unit.
Claim 7
Dependent Claim
42 words
The dual phase, dual access pipeline memory system of claim 1 in which said pipeline memory includes a plurality of memory banks, said bus means includes a plurality of data address bus pairs, and there are further included third and fourth processors.
Claim 8
Dependent Claim
77 words
The dual phase, dual access pipeline memory system of claim 6 in which said first and third processors include data fetch units which access different memory banks from each other in the same phase with each other, and said second and fourth processors include an instruction fetch unit and an I/O processor which access different memory banks from each other in the same phase with each other but out of phase with said first and third processors.
Claim 9
Dependent Claim
109 words
A multi-phase, multi-access pipeline memory system, comprising: a number, n, of processors; a pipeline memory including latch means; bus means for interconnecting said processors and pipeline memory; a clock circuit, responsive to a system clock signal for dividing said system clock signal into n phases for providing multiple clock signals corresponding to the n phases of said system clock signal for accessing each processor to allow data and address to be transferred only during its assigned phase thereby enabling said memory and each processor to operate at the system clock rate while allowing n accesses to said memory during each system clock signal period, one access for each processor.
Claim 10
Dependent Claim
109 words
A multi-phase, multi-access pipeline memory system, comprising: a number, n, of processors; a pipeline memory including latch means; bus means for interconnecting said processors and pipeline memory; a clock circuit, responsive to a system clock signal for dividing said system clock signal into n phases for providing multiple clock signals corresponding to the n phases of said system clock signal for accessing each processor to allow data and address to be transferred only during its assigned phase thereby enabling said memory and each processor to operate at the system clock rate while allowing n accesses to said memory during each system clock signal period, one access for each processor.
Claim 11
Dependent Claim
19 words
The multi-phase, multi-access pipeline memory system of claim 8 in which said processors include subprocessors in the same microprocessor.
Claim 12
Dependent Claim
23 words
The multi-phase, multi-access pipeline memory system of claim 9 in which said subprocessors include an instruction fetch unit and a data fetch unit.
Claim 13
Dependent Claim
32 words
The multi-phase, multi-access pipeline memory system of claim 8 in which said pipeline memory includes a plurality of memory banks, and said bus means includes a plurality of data address bus pairs.
Claim 14
Dependent Claim
35 words
The multi-phase, multi-access pipeline memory system of claim 8 in which said latch means includes a plurality of latches to enable pipelining of n accesses of said pipeline memory during each system clock signal period.
Claim 15
Dependent Claim
152 words
A dual phase, dual access pipeline memory system comprising: first and second processors; a pipeline memory including latch means; bus means for interconnecting said processors and pipeline memory; a clock circuit responsive to a system clock signal for providing a first clock signal in phase with said system clock signal and a second clock signal out of phase with said system clock signal for enabling said first and second processors to access memory out of phase, and a third clock signal at twice the system clock signal rate for clocking said pipeline memory by said first processors during one phase while said first processor is accessing data from the previous cycle in the same phase and, conversely, to allow an address to be supplied to said pipeline memory by said second processor during the other phase while the said second processor is accessing data from the previous cycle in the same phase.
Claim 16
Dependent Claim
152 words
A dual phase, dual access pipeline memory system comprising: first and second processors; a pipeline memory including latch means; bus means for interconnecting said processors and pipeline memory; a clock circuit responsive to a system clock signal for providing a first clock signal in phase with said system clock signal and a second clock signal out of phase with said system clock signal for enabling said first and second processors to access memory out of phase, and a third clock signal at twice the system clock signal rate for clocking said pipeline memory by said first processors during one phase while said first processor is accessing data from the previous cycle in the same phase and, conversely, to allow an address to be supplied to said pipeline memory by said second processor during the other phase while the said second processor is accessing data from the previous cycle in the same phase.
Claim 17
Dependent Claim
153 words
A dual phase, dual access pipeline memory system comprising: processor means; a pipeline memory including latch means; bus means for interconnecting said processor means and said pipeline memory; a clock circuit responsive to a system clock signal for providing a first clock signal in phase with said system clock signal, a second clock signal out of phase with said system clock signal, and a third clock signal at twice the system clock signal rate for clocking said pipeline memory through said latch means to allow an address to be supplied to said pipeline memory by said processor means during one phase while said processor means is accessing data from the previous cycle in the same phase and, conversely, to allow another address to be supplied to said pipeline memory by said processor means during the other phase while the said processor means is accessing data from the previous cycle in the same phase.
Claim 18
Dependent Claim
153 words
A dual phase, dual access pipeline memory system comprising: processor means; a pipeline memory including latch means; bus means for interconnecting said processor means and said pipeline memory; a clock circuit responsive to a system clock signal for providing a first clock signal in phase with said system clock signal, a second clock signal out of phase with said system clock signal, and a third clock signal at twice the system clock signal rate for clocking said pipeline memory through said latch means to allow an address to be supplied to said pipeline memory by said processor means during one phase while said processor means is accessing data from the previous cycle in the same phase and, conversely, to allow another address to be supplied to said pipeline memory by said processor means during the other phase while the said processor means is accessing data from the previous cycle in the same phase.
Claim 19
Dependent Claim
41 words
The dual phase, dual access pipeline memory system of claim 14 which said processor means includes a single processor issuing first and second instructions to said memory and receiving first and second data values from said memory per system clock cycle.
Claim 20
Dependent Claim
46 words
The dual phase, dual access pipeline memory system of claim 14 in which said processor means includes first and second processors and said first clock signal accesses said first processor and said second clock signal accesses said second processor out of phase with said first processor.
Claim 21
Dependent Claim
139 words
A multi-phase, multi-access pipeline memory system, comprising: a number, n, of processors each issuing two instructions and receiving two data values per system clock cycle; a number, m, of processors each issuing one instruction and receiving one data value per system clock cycle; a pipeline memory including latch means; bus means for interconnecting said processors and said pipeline memory; a clock circuit, responsive to a system clock signal, for dividing said system clock signal into 2 n+m phases for providing multiple clock signals corresponding to the 2 n+m phases of said system clock signal for accessing each processor to allow data and addresses to be transferred only during its assigned phase thereby enabling said memory and each processor to operative at the system clock rate while allowing 2 n+m accesses to said memory during each system clock signal period.
Claim 22
Dependent Claim
139 words
A multi-phase, multi-access pipeline memory system, comprising: a number, n, of processors each issuing two instructions and receiving two data values per system clock cycle; a number, m, of processors each issuing one instruction and receiving one data value per system clock cycle; a pipeline memory including latch means; bus means for interconnecting said processors and said pipeline memory; a clock circuit, responsive to a system clock signal, for dividing said system clock signal into 2 n+m phases for providing multiple clock signals corresponding to the 2 n+m phases of said system clock signal for accessing each processor to allow data and addresses to be transferred only during its assigned phase thereby enabling said memory and each processor to operative at the system clock rate while allowing 2 n+m accesses to said memory during each system clock signal period.
Claim 23
Dependent Claim
128 words
A multiple phase, multiple access pipeline memory system comprising: a pipeline memory; a number n of first type processors which access said memory twice per system clock cycle; a number m of second type processors which access said memory once per system clock cycle; means for interconnecting said processors and said pipeline memory; and a clock circuit responsive to a system clock signal for dividing the system clock signal into 2 n+m phases, two phases for each said first type of processors and one phase for each said second type of processor, each said first type processors using two phases to access said pipeline memory twice per system clock cycle, each said second type processors using one phase to access said pipeline memory once per system clock cycle.
Claim 24
Dependent Claim
128 words
A multiple phase, multiple access pipeline memory system comprising: a pipeline memory; a number n of first type processors which access said memory twice per system clock cycle; a number m of second type processors which access said memory once per system clock cycle; means for interconnecting said processors and said pipeline memory; and a clock circuit responsive to a system clock signal for dividing the system clock signal into 2 n+m phases, two phases for each said first type of processors and one phase for each said second type of processor, each said first type processors using two phases to access said pipeline memory twice per system clock cycle, each said second type processors using one phase to access said pipeline memory once per system clock cycle.
Claim 25
Dependent Claim
133 words
A dual phase, dual access pipeline memory system comprising: processor means; a pipeline memory including latch means; bus means for interconnecting said processor means and said pipeline memory; a clock circuit responsive to a system clock signal for providing a first clock cycle in phase with said system clock signal, a second clock cycle out of phase with said system clock signal, and a third cycle at twice the system clock signal rate for clocking said pipeline memory through said latch means to allow an address to be supplied to said pipeline memory by said processor means during one cycle and, conversely, to allow another address to be supplied to said pipeline memory by said processor means during the other cycle while the said processor means is accessing data from the previous cycle.
Claim 26
Dependent Claim
133 words
A dual phase, dual access pipeline memory system comprising: processor means; a pipeline memory including latch means; bus means for interconnecting said processor means and said pipeline memory; a clock circuit responsive to a system clock signal for providing a first clock cycle in phase with said system clock signal, a second clock cycle out of phase with said system clock signal, and a third cycle at twice the system clock signal rate for clocking said pipeline memory through said latch means to allow an address to be supplied to said pipeline memory by said processor means during one cycle and, conversely, to allow another address to be supplied to said pipeline memory by said processor means during the other cycle while the said processor means is accessing data from the previous cycle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-27 | 2002-01-26 | 2002-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-27 | 2006-01-26 | 2006-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-27 | 2010-01-26 | 2010-07-28 | $7700.00 | Window Closed / Lapsed |