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US5784503A Expired / Lapsed US ⏱️ 0.0 years remaining

Check reader utilizing sync-tags to match the images at the front and rear faces of a check

Assignee: Unisys Corp
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Filing: 1995-04-07
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Granted: 1998-07-21
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Expires: 2015-04-07
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Abstract

Abstract An electronic document-imaging arrangement wherein imaging means generates imaging-bits representing a given document and transfers these bits on a "per-document basis" to various successive electronic processing stages and, finally, to a data base storage unit (DBS); this arrangement also including a tag stage for creating tag bits unique for each such imaged document; these tag bits to be transferred with the imaging bits for each document to each such processing stage that handles the imaging bits, on a per document basis, and finally to DBS interface means for final matching and removal of the tag bits.

Inventors

  • 👤 John A. Bleecker, III
  • 👤 George E. Reasoner, Jr.
  • 👤 Daniel R. Edwards
  • 👤 Gerald R. Smith

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 14:35
CPC Classifications
G; G06; G06T; G06T9/00; G06T9/007

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 206 words
An electronic Front/Rear check-imaging arrangement for detecting a malfunction which throws the Front/Rear image bits out of sync comprising: imaging means which generates imaging-bits representing Front/Rear faces of a given check via digitizer means, with a common array of sync-tag bits embedded with the imaging bits for each said check in order to assure that the tag bits for such imaging bits of a given check are the same for both Front/Rear faces, these sets of imaging bits thereafter being transferred, on a "per-document basis", to various successive electronic compression and other processing stages wherein said compression is performed and completed in "real-time" and using N pairs of parallel compression paths and wherein a "FAULT" signal indicating said malfunction is generated when said sync-tag bits do not match and, operating in "real time", finally, to a data base storage means (DBS); this arrangement also including sync-tag means constructed to create said sync-tag bits unique for each such imaged check-face and to transfer these sync-tag bits with the imaging bits for both check faces to each such processing stage for handling the Front/Rear imaging bits, on a per document basis, and finally to DBS interface means for final matching between faces, and removal of the sync-tag bits.
Claim 2
Dependent Claim 206 words
An electronic Front/Rear check-imaging arrangement for detecting a malfunction which throws the Front/Rear image bits out of sync comprising: imaging means which generates imaging-bits representing Front/Rear faces of a given check via digitizer means, with a common array of sync-tag bits embedded with the imaging bits for each said check in order to assure that the tag bits for such imaging bits of a given check are the same for both Front/Rear faces, these sets of imaging bits thereafter being transferred, on a "per-document basis", to various successive electronic compression and other processing stages wherein said compression is performed and completed in "real-time" and using N pairs of parallel compression paths and wherein a "FAULT" signal indicating said malfunction is generated when said sync-tag bits do not match and, operating in "real time", finally, to a data base storage means (DBS); this arrangement also including sync-tag means constructed to create said sync-tag bits unique for each such imaged check-face and to transfer these sync-tag bits with the imaging bits for both check faces to each such processing stage for handling the Front/Rear imaging bits, on a per document basis, and finally to DBS interface means for final matching between faces, and removal of the sync-tag bits.
Claim 3
Dependent Claim 19 words
The invention of claim 1, wherein said tag bits are checked at some or all of said processing states.
Claim 4
Dependent Claim 18 words
The invention of claim 2, wherein said tag bits are embedded with the imaging bits for each check.
Claim 5
Dependent Claim 67 words
The invention of claim 3, wherein two or more imaging means are involved, each generating a respective set of imaging bits, with a common array of tag bits for each said check, these sets of imaging bits thereafter being presented to interface means, including compare means, to assure that the tag bits for such imaging bits of a given check are the same for both Front/Rear Faces.
Claim 6
Dependent Claim 40 words
The invention of claim 4, wherein said imaging means constitute Front and Rear camera means generating respective Front and Rear sets of imaging bits, each set being merged with common related set of tag bits uniquely identifying the common check.
Claim 7
Dependent Claim 68 words
The invention of claim 5, wherein said Front and Rear sets of imaging bits/tag bits are transferred to common processor stages via a single transfer stage (DT), along with "collateral bits" including "status bits" and wherein this transfer stage DT reads and checks each pair of tag bits before transferring the image bits/tag bits onward and causes a "FAULT" signal to be generated when they do not match.
Claim 8
Dependent Claim 35 words
The invention of claim 6, wherein all said pairs of bits are stored in Queue means in such transfer stage, and said transfer stage automatically issues INTERRUPT wherever its said Queue means is "Not Empty".
Claim 9
Dependent Claim 32 words
The invention of claim 7, wherein associated program means is adapted to generate said tag bits and to monitor the match thereof before allowing a "valid" final transfer to said storage means.
Claim 10
Dependent Claim 17 words
The invention of claim 8, wherein such "status bits" are also transferred with their associated image bits.
Claim 11
Dependent Claim 37 words
The invention of claim 1, wherein said electronic processing stages include a Histogram/Compressor stage (1/C) fed by Normalizing/Scaling means (N/S), and wherein said tag bits are transferred to said N/S means and thence to said H/C means.
Claim 12
Dependent Claim 32 words
The invention of claim 9, wherein said tag-bits are so transferred along with respective status bits, after the final scan of a check, using the same bus as for said imaging bits.
Claim 13
Dependent Claim 27 words
The invention of claim 10, wherein said N/S means includes "Last set register" means for storage of respective tag bits and later transfer to said H/C means.
Claim 14
Dependent Claim 32 words
The invention of claim 11, wherein said image bits are JPEG data bits and are input from said stage (H/C) to JPEG Data Buffer means in route to said final storage means.
Claim 15
Dependent Claim 24 words
The invention of claim 12, wherein said N/S means include Tag Register means input from DT interface means and output to H/C interface means.
Claim 16
Dependent Claim 21 words
The invention of claim 14, wherein said N/S means also includes "Last tag" register means input to said DT interface means.
Claim 17
Dependent Claim 18 words
The invention of claim 15, wherein said N/S means also includes Fault register means and Status register means.
Claim 18
Dependent Claim 35 words
The invention of claim 15, wherein said DT interface means includes Queue means adapted to automatically be interrupted when "Not empty" and to periodically remove the data at the head of said Tag Register means.
Claim 19
Dependent Claim 28 words
The invention of claim 16, wherein said stage (H/C) means is coupled to Compressed Image Data buffer means which, in turn, is coupled to input JPEG Buffer means.
Claim 20
Dependent Claim 22 words
The invention of claim 18, wherein both said buffer means are adapted to also store "status bits" with each imaging/tag bit set.
Claim 21
Dependent Claim 55 words
The invention of claim 14, wherein said N/S means comprises Master N/S, Means and Slave N/S means, each coupled to receive associated imaging/tag bits in parallel, and both are coupled to common compare means adapted to issue a "FAULT" signal if the tag bits therein do not match for a given set of imaging bits.
Claim 22
Dependent Claim 15 words
The invention of claim 18, wherein said "Status bits" are transferred with said imaging bits.

References Cited (Backward Citations)

US4523330A Cited
US5329616A Cited
US5157740A Cited
US5134661A Cited
US5164993A Cited
US5528705A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-07-20 2002-01-19 2002-07-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-07-20 2006-01-19 2006-07-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-07-20 2010-01-19 2010-07-21 $7700.00 Window Closed / Lapsed

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