US5784497A
Expired / Lapsed
US
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Arithmetic encoding with carry over processing
Assignee: Canon Inc
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Filing: 1996-03-06
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Granted: 1998-07-21
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Expires: 2016-03-06
Abstract
Abstract An image encoding device for effecting the carryover process on a real-time basis in arithmetic encoding, and without interruption in the function of the arithmetic encoder. The device is provided with an encoder for outputting code data, encoded by arithmetic codes, in succession by a predetermined number of bits, shift registers for retaining plural sets of the code data output from the encoder, and a processor for applying a carry-over process to the thus retained plural sets of code data.
Inventors
- 👤 Keiji Ishizuka
- 👤 Atsushi Furuya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:57
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/41; H04N1/411; H04N1/413; H04N1/417; H03; H03M; H03M7/00; H03M7/30; H03M7/40; H03M7/4006
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
367 words
An image encoding device comprising: encoding means for encoding image data based on an arithmetic code to generate code data composed of "0" and "1"; output means for outputting the code data by a predetermined number of bits in parallel and carry-over data of one bit indicating whether there is a carry-over; determining means for determining whether or not all bits of the code data of the predetermined number of bits are "1"s and outputting determination data of one bit indicating whether all bits are "1"; a plurality of serially connected code latch means, each of which latches the code data of the predetermined number of bits, the code data of the predetermined number of bits being shifted in parallel through said plurality of code latch means; a plurality of serially connected first data latch means, each of which latches the carry-over data of one bit corresponding to each of said plurality of code latch means, the carry-over data of one bit being shifted through said plurality of first data latch means in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch means; a plurality of serially connected second data latch means, each of which latches the determination data of one bit corresponding to each of said plurality of code latch means, the determination data of one bit being shifted through said plurality of second data latch means in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch means; carry-over process means for effecting a carry-over process on the code data latched in said plurality of code latch means based on the carry-over data latched in said plurality of first data latch means and the determination data latched in said plurality of second latch means; and adding means for adding the carry-over data of one-bit shifted through said plurality of first data latch means and the code data of the predetermined number of bits shifted in parallel through said plurality of code latch means, so as to output a result of the addition as established code data of the predetermined number of bits.
Claim 2
Dependent Claim
367 words
An image encoding device comprising: encoding means for encoding image data based on an arithmetic code to generate code data composed of "0" and "1"; output means for outputting the code data by a predetermined number of bits in parallel and carry-over data of one bit indicating whether there is a carry-over; determining means for determining whether or not all bits of the code data of the predetermined number of bits are "1"s and outputting determination data of one bit indicating whether all bits are "1"; a plurality of serially connected code latch means, each of which latches the code data of the predetermined number of bits, the code data of the predetermined number of bits being shifted in parallel through said plurality of code latch means; a plurality of serially connected first data latch means, each of which latches the carry-over data of one bit corresponding to each of said plurality of code latch means, the carry-over data of one bit being shifted through said plurality of first data latch means in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch means; a plurality of serially connected second data latch means, each of which latches the determination data of one bit corresponding to each of said plurality of code latch means, the determination data of one bit being shifted through said plurality of second data latch means in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch means; carry-over process means for effecting a carry-over process on the code data latched in said plurality of code latch means based on the carry-over data latched in said plurality of first data latch means and the determination data latched in said plurality of second latch means; and adding means for adding the carry-over data of one-bit shifted through said plurality of first data latch means and the code data of the predetermined number of bits shifted in parallel through said plurality of code latch means, so as to output a result of the addition as established code data of the predetermined number of bits.
Claim 3
Dependent Claim
60 words
A device according to claim 1, wherein said carry-over process means effects the carry-over process on the code data latched in said code latch means corresponding to said second data latch means which latches the determination data indicating that all bits of the code data are "1"s in accordance with the carry-over data latched in said first data latch means.
Claim 4
Dependent Claim
93 words
A device according to claim 2, wherein in a case where the carry-over data is output from said outputting means after the code data of which all bits are "1"s is output from said outputting means and is latched in a first stage of said code latch means, said carry-over process means causes a second stage of said code latch means to latch code data of which all bits are "0"s and causes said first data latch means corresponding to the second stage of said code latch means to latch the carry-over data.
Claim 5
Dependent Claim
105 words
A device according to claim 2, wherein in a case where the carry-over data is latched in said first data latch means corresponding to said code latch means before said code latch means which latches the code data of which all bits are "1"s, said carry-over process means causes said code latch means which latches the code data of which all bits are "1" to latch code data of which all bits are "0"s and causes said data latch means corresponding to said code latch means which is caused to latch the code data of which all bits are "0"s to latch the carry-over data.
Claim 6
Dependent Claim
298 words
An image encoding device comprising: encoding means for encoding image data based on an arithmetic code to generate code data composed of "0" and "1"; output means for outputting the code data by a predetermined number of bits in parallel and carry-over data of one bit indicating whether there is a carry-over; a plurality of serially connected code latch means, each of which latches the code data of the predetermined number of bits, the code data of the predetermined number of bits being shifted in parallel through said plurality of code latch means; a plurality of serially connected data latch means, each of which latches the carry-over data of one bit corresponding to each of said plurality of code latch means, the carry-over data of one bit being shifted through said plurality of data latch means in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch means: a plurality of determining means, each of which determines whether or not all bits of the code data of the predetermined number of bits latched in an associated one of said plurality of code latch means are "1"s; carry-over process means for effecting a carry-over process on the code data latched in said plurality of code latch means based on the carry-over data latched in said plurality of data latch means and the determination results of said plurality of determining means; and adding means for adding the carry-over data of one bit shifted through said plurality of data latch means and the code data of the predetermined number of bits shifted in parallel through said plurality of code latch means, so as to output a result of the addition as established code data of the predetermined number of bits.
Claim 7
Dependent Claim
298 words
An image encoding device comprising: encoding means for encoding image data based on an arithmetic code to generate code data composed of "0" and "1"; output means for outputting the code data by a predetermined number of bits in parallel and carry-over data of one bit indicating whether there is a carry-over; a plurality of serially connected code latch means, each of which latches the code data of the predetermined number of bits, the code data of the predetermined number of bits being shifted in parallel through said plurality of code latch means; a plurality of serially connected data latch means, each of which latches the carry-over data of one bit corresponding to each of said plurality of code latch means, the carry-over data of one bit being shifted through said plurality of data latch means in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch means: a plurality of determining means, each of which determines whether or not all bits of the code data of the predetermined number of bits latched in an associated one of said plurality of code latch means are "1"s; carry-over process means for effecting a carry-over process on the code data latched in said plurality of code latch means based on the carry-over data latched in said plurality of data latch means and the determination results of said plurality of determining means; and adding means for adding the carry-over data of one bit shifted through said plurality of data latch means and the code data of the predetermined number of bits shifted in parallel through said plurality of code latch means, so as to output a result of the addition as established code data of the predetermined number of bits.
Claim 8
Dependent Claim
36 words
A device according to claim 5, wherein said carry-over process means effects the carry-over process on the code data of which all bits are "1"s in accordance with the determination of said plurality of determining means.
Claim 9
Dependent Claim
353 words
An image encoding method comprising: an encoding step of encoding image data based on an arithmetic code to generate code data composed of "0" and "1"; an output step of outputting the code data by a predetermined number of bits in parallel and carry-over data of one bit indicating whether there is a carry-over; a determining step of determining whether or not all bits of the code data of the predetermined number of bits are "1"s and outputting determination data of one bit indicating whether all bits are "1"; a first shifting step of shifting in parallel the code data of the predetermined number of bits through a plurality of serially connected code latch devices, each of which latches the code data of the predetermined number of bits; a second shifting step of shifting the carry-over data of one bit through a plurality of serially connected first data latch devices in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch devices, each of which first data latch devices latches the carry-over data of one bit; a third shifting step of shifting the determination data of one bit through a plurality of serially connected second data latch devices in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch devices, each of which second data latch devices latches the determination data of one bit; a carry-over process step of effecting a carry-over process on the code data latched in the plurality of code latch devices based on the carry-over data latched in the plurality of first data latch devices and the determination data latched in the plurality of second latch devices: and an adding step of adding the carry-over data of one bit shifted through the plurality of first data latch devices and the code data of the predetermined number of bits shifted in parallel through the plurality of code latch devices, so as to output a result of the addition as established code data of the predetermined number of bits.
Claim 10
Dependent Claim
353 words
An image encoding method comprising: an encoding step of encoding image data based on an arithmetic code to generate code data composed of "0" and "1"; an output step of outputting the code data by a predetermined number of bits in parallel and carry-over data of one bit indicating whether there is a carry-over; a determining step of determining whether or not all bits of the code data of the predetermined number of bits are "1"s and outputting determination data of one bit indicating whether all bits are "1"; a first shifting step of shifting in parallel the code data of the predetermined number of bits through a plurality of serially connected code latch devices, each of which latches the code data of the predetermined number of bits; a second shifting step of shifting the carry-over data of one bit through a plurality of serially connected first data latch devices in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch devices, each of which first data latch devices latches the carry-over data of one bit; a third shifting step of shifting the determination data of one bit through a plurality of serially connected second data latch devices in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch devices, each of which second data latch devices latches the determination data of one bit; a carry-over process step of effecting a carry-over process on the code data latched in the plurality of code latch devices based on the carry-over data latched in the plurality of first data latch devices and the determination data latched in the plurality of second latch devices: and an adding step of adding the carry-over data of one bit shifted through the plurality of first data latch devices and the code data of the predetermined number of bits shifted in parallel through the plurality of code latch devices, so as to output a result of the addition as established code data of the predetermined number of bits.
Claim 11
Dependent Claim
60 words
A method according to claim 7, wherein the carry-over process step effects the carry-over process on the code data latched in the code latch device corresponding to the second data latch device which latches the determination data indicating that all bits of the code data are "1"s in accordance with the carry-over data latched in the first data latch devices.
Claim 12
Dependent Claim
94 words
A method according to claim 8, wherein in a case where the carry-over data is output in said output step after the code data of which all bits are "1"s is output in said output step and is latched in a first stage of the code latch device, said carry-over process step causes a second stage of the code latch device to latch the code data of which all bits are "0"s and causes the first data latch device corresponding to the second stage of the code latch device to latch the carry-over data.
Claim 13
Dependent Claim
106 words
A method according to claim 8, wherein in a case where the carry-over data is latched in the first data latch device corresponding to the code latch device before the code latch device which latches the code data of which all bits are "1"s, said carry-over process step causes the code latch device which latches the code data of which all bits are "1" to latch code data of which all bits are "0"s and causes the first data latch device corresponding to the code latch device which is caused to latch the code data of which all hits are "0"s to latch the carry-over data.
Claim 14
Dependent Claim
284 words
An image encoding method comprising: an encoding step of encoding image data based on an arithmetic code to generate code data composed of "0" and "1"; an output step of outputting the code data by a predetermined number of bits in parallel and carry-over data of one bit indicating whether there is a carry-over; a first shifting step of shifting in parallel the code data of the predetermined number of bits through a plurality of serially connected code latch devices, each of which latches the code data of the predetermined number of bits; a second shifting step of shifting the carry-over data of one bit through a plurality of serially connected data latch devices in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch devices, each of which data latch devices latches the carry-over data of one bit, a determining step of determining whether or not all bits of the code data of the predetermined number of bits latched in each of the plurality of code latch devices are "1"s; a carry-over process step of effecting a carry-over process on the code data latched in the plurality of code latch devices in accordance with the carry-over data latched in the plurality of data latch devices and the determination results of said determining step; and an adding step of adding the carry-over data of one bit shifted through the plurality of data latch devices and the code data of the predetermined number of bits shifted in parallel through the plurality of code latch devices, so as to output a result of the addition as established code data of the predetermined number of bits.
Claim 15
Dependent Claim
284 words
An image encoding method comprising: an encoding step of encoding image data based on an arithmetic code to generate code data composed of "0" and "1"; an output step of outputting the code data by a predetermined number of bits in parallel and carry-over data of one bit indicating whether there is a carry-over; a first shifting step of shifting in parallel the code data of the predetermined number of bits through a plurality of serially connected code latch devices, each of which latches the code data of the predetermined number of bits; a second shifting step of shifting the carry-over data of one bit through a plurality of serially connected data latch devices in synchronism with the parallel shift of the code data of the predetermined number of bits through the plurality of code latch devices, each of which data latch devices latches the carry-over data of one bit, a determining step of determining whether or not all bits of the code data of the predetermined number of bits latched in each of the plurality of code latch devices are "1"s; a carry-over process step of effecting a carry-over process on the code data latched in the plurality of code latch devices in accordance with the carry-over data latched in the plurality of data latch devices and the determination results of said determining step; and an adding step of adding the carry-over data of one bit shifted through the plurality of data latch devices and the code data of the predetermined number of bits shifted in parallel through the plurality of code latch devices, so as to output a result of the addition as established code data of the predetermined number of bits.
Claim 16
Dependent Claim
45 words
A method according to claim 11, wherein said carry-over process step effects the carry-over process on the code data of which all bits are "1"s in accordance with the determination result of said determining step and the carry-over data latched in the data latch devices.
Claim 17
Dependent Claim
71 words
A method according to claim 11, wherein in a case where the carry-over data is output in said output step after the code data of which all bits are "1"s is output in said output step and is latched in a first state of the code latch device, said carry-over process step causes a second stage of the code latch device to latch code data of which all bits are "0"s.
Claim 18
Dependent Claim
73 words
A method according to claim 11, wherein in a case where the carry-over data is latched in the data latch device corresponding to the code latch device before the code latch device which latches the code data of which all bits are "1"s, said carry-over process step causes the code latch device which latches the code data of which all bits are "1" to latch code data of which all bits are "0"s.
Claim 19
Dependent Claim
71 words
A device according to claim 5, wherein in a case where the carry-over data is output from said outputting means after the code data of which all bits are "1"s is output from said outputting means and is latched in a first stage of said code latch means, said carry-over process means causes a second stage of said code latch means to latch code data of which all bits are "0"s.
Claim 20
Dependent Claim
73 words
A device according to claim 5, wherein in a case where the carry-over data is latched in said data latch means corresponding to said code latch means before said code latch means which latches the code data of which all bits are "1"s, said carry-over process means causes said code latch means which latches the code data of which all bits are "1" to latch code data of which all bits are "0"s.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-20 | 2002-01-19 | 2002-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-20 | 2006-01-19 | 2006-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-20 | 2010-01-19 | 2010-07-21 | $7700.00 | Window Closed / Lapsed |